Senior DDR5/DDR6 PHY Engineering Lead
Renesas
Renesas is looking for a Senior Analog Engineering Manager in Austin, Texas, to lead the development of DDR5 and next-generation DDR6 PHY solutions. The role demands extensive technical expertise and proven leadership skills to manage a team focusing on high-performance, low-power DDR PHYs. The successful candidate will oversee the entire process from architecture to silicon bring-up, ensuring compliance with industry standards while mentoring engineers and managing program execution. Experience in high-speed memory interfaces is crucial. #J-18808-Ljbffr Renesas
Vacancy posted 16 hours ago
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