Senior DDR5/LPDDR5 Memory Validation Lead
$149.1k - $215kAltera
Altera in San Jose is seeking a highly skilled DDR5 / LPDDR5 Memory Validation Engineer to lead validation and debug activities for advanced memory interfaces on cutting-edge FPGA devices. The role requires significant industry experience in memory subsystem validation and strong collaboration skills across multiple teams. The salary range is $149,100 - $215,000 USD, with additional incentive opportunities. #J-18808-Ljbffr Altera
Vacancy posted 3 days ago
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