Senior UVM Verification Lead (SystemVerilog)
$170kArtha Nexgen
Artha Nexgen is seeking a UVM Lead Verification Engineer in Seattle to lead a design verification team at a customer location. The role requires expertise in System Verilog and UVM, with a focus on developing UVM testbenches and managing a team. Candidates should have 8 years of experience in the field with strong debugging skills. The position is full-time, offering a competitive salary of $170k annually. #J-18808-Ljbffr Artha Nexgen
Vacancy posted 18 hours ago
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