Memory & Custom Library Layout Lead — PPA & RTL Integration
NUVACORE
NUVACORE is seeking a Custom Library and Memory Layout Lead to drive the layout of custom cells and memory arrays at advanced CMOS nodes. You will own end-to-end layout closure—from floorplanning to parasitic extraction—and collaborate with circuit design, foundry, CAD, and DFT teams to optimize PPA and manufacturability. You will define layout methodology, build automation, and manage layout vendors to scale production across macro and cell designs. #J-18808-Ljbffr NUVACORE
Vacancy posted 13 hours ago
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