Sr FPGA Engineer

Job Summary The Senior Digital and FPGA Engineer is responsible for designing and developing new FPGAs for IPG lasers, scanners, and LDD inspection systems. This role includes hands on lab debugging, integration, and testing. The engineer will also collaborate closely with the Hardware and Software Engineering teams to develop innovative system solutions from concept through to production release. Key Responsibilities Independently lead complex FPGA development projects from concept through production using Intel/Altera and AMD/Xilinx FPGA, SoC, MPSoC, and RFSoC platforms. Design and implement FPGA-based motion control solutions for XYZ stages, rotary stages, galvanometers, and other precision positioning systems. Develop advanced FPGA algorithms for electro-optical systems, including optical scan control (OSC), high-speed signal processing, machine vision, and real-time control applications. Perform hands‑on system integration, bring‑up, and troubleshooting of complex electro‑optical systems, leveraging broad experience across optics, mechanics, electronics, FPGA development, and software engineering. Design, implement, debug, and support complex electro‑optical and electromechanical systems operating under real‑time FPGA control. Develop FPGA architecture, RTL, verification environments, simulation infrastructure, and hardware validation test platforms. Build and maintain automated CI/CD pipelines for FPGA verification, testing, quality metrics, and release management. Leverage AI‑assisted engineering tools to accelerate FPGA development, verification, software development, documentation, root‑cause analysis, and system‑level debugging. Apply broad cross‑disciplinary expertise in FPGA design, embedded systems, software engineering, manufacturing, and production support to solve complex engineering challenges and accelerate product development. Requirements Bachelor's degree in Engineering required; Master's degree preferred. Electrical Engineering preferred. 5+ years of FPGA RTL development experience using Verilog and SystemVerilog. 3+ years of software development experience in C, C++, C#, Python, or similar. Strong hands‑on experience with QuestaSim, Vivado, and Quartus development environments. Proven ability to design and develop complex FPGA‑based systems from concept through production, including RTL design, verification, timing closure, bitstream generation, hardware bring‑up, and production support. Experience implementing DSP and MATLAB algorithms in FPGA hardware is highly desirable. Experience integrating FPGA designs with ARM‑based SoCs running Linux. Solid understanding of clock domain crossing (CDC), synchronization techniques. Proficiency with Git and modern CI/CD development workflows. Experience leveraging AI‑assisted engineering tools to improve development productivity. Strong analytical and problem‑solving skills with the ability to work independently on complex technical challenges. Location(s) 377 Simarano Drive, Marlborough, Massachusetts 01752, United States Employment Type Exempt Wage Information MA: $112,436 - $130,707 US Benefits Information Pay Range The pay range on this posting applies to the role in the primary location specified. If the candidate would ultimately work outside of the primary location posted, the applicable range could differ. Actual starting pay is determined by a number of factors including relevant skills, qualifications, and experience. Other Compensation Annual Discretionary Bonus or Sales Bonus as Applicable Benefits Provided Paid vacation time accrued based on years of service *Prorated for reduced hour schedules Additional Benefits Offered Medical, dental, and vision insurance plans with options for HSA/FSA Dependent Care FSA Paid Basic Life and AD&D Insurance Short-term and Long-term Disability insurance 401(k) plan with Company matching Employee Stock Purchase Plan (ESPP) Tuition Reimbursement Program Employee Assistance Program (EAP) Adoption Assistance Pet Insurance Bright Horizons Backup Care Bright Horizons College Coach *Benefits eligibility may differ by program for reduced hour schedules #J-18808-Ljbffr