Senior ASIC Timing Architect for Full-Chip SoC
$165k - $241.4kCisco Systems
Cisco Systems, Inc. is seeking an experienced engineer for their Silicon One team in San Jose, CA. The role focuses on developing full-chip timing constraints for networking SoCs, driving Static Timing Analysis, and collaborating with cross-functional teams to ensure timing correctness. The ideal candidate will possess a Bachelor’s degree in Electrical or Computer Engineering and extensive experience in ASIC design. A competitive salary range between $165,000 and $241,400 is offered, alongside a range of comprehensive benefits including a flexible vacation policy. #J-18808-Ljbffr Cisco Systems, Inc.
Vacancy posted 3 days ago
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