Senior ASIC DV Engineer - SOC Verification & UVM Expert
$127.1k - $226kBroadcom Inc.
A leading semiconductor company is seeking a Senior ASIC DV Engineer to develop complex SOCs for Touch Controllers and Wireless Charging Chips. The role requires expertise in architecting verification environments, debugging simulations, and low power silicon verification. Candidates should have a strong educational background, with an emphasis on related experience, while enjoying a competitive salary between $127,100 - $226,000 and comprehensive benefits, including a discretionary bonus and equity opportunities. #J-18808-Ljbffr Broadcom Inc.
- Mirafra Technologies is seeking a skilled SoC Verification Engineer in San Jose, California. The ideal candidate will have 8-12 years of experience, with strong proficiency in SV Assertions and scripting languages such as TCL and Python. You will work on verifying complex...Senior
- NVIDIA Corporation is hiring a Senior ASIC Verification Engineer in Santa Clara, California. This position involves... ...and implementations of cutting-edge SoCs and GPUs, along with defining... ...and be proficient in SystemVerilog and UVM. The role provides a competitive salary...Senior
- A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, California. This role involves building and verifying timing constraints for large SoCs, requiring expertise in SDC development and EDA tools, particularly Synopsys Design Compiler and Primetime...Senior
- ...innovative high-tech startup in Santa Clara seeks a Senior Design Verification Engineer to architect and develop verification... ...candidate will have extensive experience in ASIC verification, strong skills in SystemVerilog and UVM, and a passion for solving complex problems....Senior
$127.1k - $226k
Senior ASIC DV Engineer page is loaded## Senior ASIC DV Engineerlocations: USA-CA... ...the development of complex SOCs targeted towards Touch Controllers... ...other new initiatives. As a verification engineer, your... ...verification environments using HVLs (UVM) and constrained random...SeniorLocal area$136k - $218.5k
Senior ASIC Verification Engineer page is loaded## Senior ASIC Verification Engineerlocations... ...of the world’s leading SoC's and GPU's. This position offers... ...infrastructure, DV strategies and test-planning... ...proficient in SystemVerilog/UVM.* Familiarity with memory subsystem...Senior$136k - $218.5k
...seeking outstanding Senior Design Verification Engineers with a specialty in tools... ...supercomputers.Our DV infrastructure and... ...computer architecture, ASIC design, and verification... ...methodology (UVM or similar)* Exposure... ...IP to multiple GPUs/SoCs in parallel* Experience...Senior$225k
Frey Consulting Group is seeking 4 experienced ASIC/VLSI Engineers for permanent, full-time, onsite roles in Silicon Valley. The successful candidates will support advanced semiconductor and AI/networking programs with tier-1 clients. Key requirements include 8+ years of...SeniorPermanent employmentFull time$153.2k - $229.8k
A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree...Senior- A leading technology company in Santa Clara is looking for a Design Verification Engineer to ensure the functionality and performance of their SOCs. The role involves developing test plans, collaborating with design teams, and verifying various hardware components. The...Senior
$110k - $300k
A leading technology company in San Jose, California, is looking for a skilled engineer specializing in SoC design verification. The ideal candidate should hold an MS or PhD in Electrical Engineering with extensive experience in verification methodologies. Responsibilities...Senior$106.4k - $172.15k
Palo Alto Networks, Inc. is seeking a Design Verification Engineer for our ASIC team in Santa Clara, California. This role focuses on ensuring next-generation firewall products meet performance and reliability standards. You will define verification methodologies, architect...Senior$169.7k - $315.1k
Rambus.com is seeking an exceptional SPE Verification Engineer to join our Memory Interface Chip team in San Jose. In this role, you will develop verification environments and collaborate with teams to ensure chip quality throughout the design process. Offering a flexible...SeniorFlexible hours- ...impact MTS Design Verification Engineer with strong technical... ...high‑performance ASIC designs. The ideal... ..., subsystem, and SoC levels. You will... ...Development Develop robust UVM‑based testbench... ...& TOOLS Required Expert‑level knowledge of... ...and guide junior DV engineers....
- ...unique experience for ASIC engineers by combining the resources... ...in the ASIC design verification for Cisco high-end switching... ...Design Verification (DV) environment... ...in System Verilog and UVM. Experience with ASIC... ...protocols and large‑scale SoC architectures #J-18808...Senior
- ...Job Description Job Description Senior ASIC Verification Engineer (AI Hardware) — Remote (U.S.) — No Visa... ...environments using System Verilog and UVM Create simulation infrastructure, including... ...of hands-on experience in ASIC or SoC verification Strong proficiency...SeniorRemote workVisa sponsorship
$250k - $280k
...Sunnyvale is seeking a Principal Design Verification Engineer to lead a team in the verification of complex IPs and SoCs. The ideal candidate should have... ...12 to 15 years of experience in ASIC design verification, expertise in SystemVerilog and UVM methodology, and strong...Senior- ...pioneering technology firm in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to ensure the functional correctness of high-speed low-power... ...experience in ASIC verification, particularly using UVM and SystemVerilog. Responsibilities include developing testbenches...Senior
$165k - $241.4k
Cisco Systems, Inc. is hiring for an ASIC Verification role based in San Jose, CA. The position requires leading verification methodology and... ...teams. Ideal candidates should have experience in System Verilog, UVM, and team leadership. With a competitive salary ranging from $...Senior$116k - $189.75k
NVIDIA Corporation in Santa Clara is seeking an ASIC Clocks Verification Engineer to collaborate with ASIC designers and verification engineers. You will... ...Engineering and practical experience with SystemVerilog, UVM, and strong scripting skills in Python or Perl. The...Senior$168k - $264.5k
Senior Verification Engineer - Hardware page is loaded Senior Verification Engineer... ..., Accelerated UVM Testbenches). Bring up SOCs on emulation, root causing... ...collaboration with Design, DV, Power, Silicon Validation... ...Similar Jobs (5) Senior ASIC Design Engineer - Hardware...SeniorFull timeWorldwideFlexible hours- ...Systems, Inc. in San Jose, California is seeking an experienced ASIC Design Verification Engineer to participate in the verification of high-end switching... ...will have a deep understanding of System Verilog and UVM, along with extensive experience in ASIC design. This role...Senior
- L&T Technology Services Limited is seeking an experienced engineer with over 5 years of hands-on expertise in DFT and ATPG for SoC or ASIC designs. The candidate should have a strong understanding of DFT fundamentals, including controllability, observability, and scan-...Senior
- ...Description Job Description POSITION: Senior DV Engineer Who We Are: Quest Global... ...and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role... ...Express etc. ○ Strong in HVL (UVM / SystemVerilog / OVM), C/C++,...SeniorRemote work
$178k - $389k
Micron Technology, Inc is seeking an experienced verification engineer in San Jose, CA. This role involves owning pre-silicon functional verification... ...-speed interface chips, including building and maintaining UVM/SystemVerilog testbenches. Candidates should have 6-12 years...Senior- ...Jose, California is seeking an experienced design engineer to handle the physical implementation of SOC projects. This position requires a minimum of 10 years... ...will possess expertise in design optimization and verification, aiming for best power, performance, and area....Senior
$156k - $229k
...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...years of experience with design verification. Experience with SystemVerilog... ...with three or more SoC projects/cycles. About the job... ...exceptional verification. Using your UVM and SystemVerilog coding and...SeniorFull timeWorldwide$126.8k - $220.9k
A leading technology company in Sunnyvale, California seeks a Wireless PHY Design Verification Engineer to develop and implement advanced verification strategies for WiFi SoCs. The role demands sophisticated test environments and strong experience in wireless and DSP systems...- Intel Corporation is seeking a SOC Design Verification Engineer in Santa Clara, California to perform functional logic verification of integrated SoCs. If you’re passionate about innovation and have strong experience with verification methodologies, we want you on our...Senior
$181.1k - $318.4k
...leading technology company in Cupertino is seeking an experienced professional to join its Emulation verification team. The role involves working on verifying large SoCs and collaborating with various teams. Ideal candidates should have at least 10 years of experience,...Senior
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