Principal EDA Engineer

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on LinkedIn and X.ADI is seeking a Principal EDA Engineer with deep expertise in Calibre-based physical verification, code development, and tapeout support for advanced analog and mixed-signal programs. This role serves as a technical authority for signoff methodology, rule deck implementation, verification flow development, and critical tapeout readiness across multiple projects and process nodes. The engineer in this role will lead the development and optimization of Calibre-driven flows, build code and tools that extend verification capability, and partner closely with design and layout teams to resolve high-impact issues from project setup through final signoff.Key ResponsibilitiesCalibre Technical Authority: Serve as a recognized expert for Calibre-based physical verification flows, including DRC, LVS, ERC, PERC, parasitic extraction, and signoff methodologyVerification Flow Development: Define, develop, maintain, and optimize Calibre verification flows and supporting infrastructure for analog and mixed-signal design teamsRule Deck and Code Development: Write, debug, and enhance SVRF and TVF rule sets, along with custom code and scripts that extend Calibre capabilities, improve debug efficiency, and strengthen flow reliabilityTapeout Support Leadership: Lead or guide tapeout readiness activities, including final signoff checks, waiver management, antenna-related issue resolution, deliverable preparation, and coordination of critical verification closure itemsFoundry Rule Integration: Drive intake, validation, integration, and versioning of foundry rule files and process updates for advanced-node programsCritical Debug and Escalation: Resolve the most complex verification, runset, extraction, and rule deck issues affecting project execution or tapeout schedulesProject Enablement: Support new project setup, verification environment readiness, and early issue identification so design teams can avoid downstream signoff riskTooling and Automation: Build internal tools, scripts, dashboards, and reporting utilities that improve verification visibility, XOR analysis, runtime efficiency, and license or compute usageTechnical Guidance and Mentorship: Provide training, documentation, and expert guidance to engineers using verification flows and signoff methodologies across the organizationMust Have SkillsCalibre Expertise: Expert-level proficiency with Mentor Calibre across DRC, LVS, ERC, PERC, extraction, and signoff flowsRule Deck Development: Deep hands-on experience writing, debugging, and maintaining SVRF and TVF rule sets for advanced-node verificationCode and Tool Development: Strong experience developing code, scripts, and internal tools that utilize and extend Calibre workflows, including automation, result parsing, analysis, and debug supportTapeout and Signoff Support: Proven experience supporting tapeouts, final verification closure, waiver flows, antenna-related issues, and foundry-facing signoff requirementsAdvanced Node Experience: Strong experience with TSMC design rules, rule deck integration, and physical verification challenges at nodes such as 16nm, 5nm, and 4nmDebug Leadership: Ability to lead resolution of complex backend verification and extraction issues with significant project or schedule impactEDA Environment Knowledge: Strong understanding of Linux-based EDA environments, compute infrastructure, license usage, and version-controlled design data workflowsCross-Functional Technical Support: Ability to work effectively with analog layout, design, CAD, and project teams in a fast-paced multi-project environmentAnalog Physical Design Understanding: Strong understanding of analog layout practices, physical verification issues, and signoff expectationsPreferred Education and ExperienceBS or MS in Electrical Engineering, Computer Engineering, or a related field, or an equivalent combination of education and 10+ years of related experienceExperience supporting digital physical design or place-and-route verification flowsExperience with Perforce for design data managementExperience with Cadence Virtuoso customization, including SKILL, bindkeys, or layout environment setupExperience building GUI-based tools, reporting systems, or verification analytics dashboardsExperience with EDA license management, compute optimization, or multi-site verification infrastructureFamiliarity with AI-assisted methods that improve verification productivity, debug efficiency, or flow effectivenessWe recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.#LI-PG1For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.EEO is the Law: Notice of Applicant Rights Under the Law.Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $159,638 to $239,457.Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.SummaryLocation: US, MA, Wilmington; US, NC, DurhamType: Full time