FPGA Engineer

About Cowboy Space CorpMission Cowboy Space Corporation is solving the global energy crisis by building the infrastructure for abundant, resilient space-based solar energy. We are tackling one of humanity’s most complex engineering challenges with a world-class team dedicated to delivering a revolutionary power platform. Cowboy Space Corporation is transforming how civilization powers, computes and connects - from orbit to Earth. Background Cowboy Space Corporation is building the infrastructure to power and connect the orbital economy. Our modular, scalable satellites collect sunlight in Low Earth Orbit to enable multiple integrated applications: transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit high-performance computing clusters (GPU/TPU), and providing secure, high bandwidth optical data transport. Current energy and data systems rely on complex logistics and outdated infrastructure. Cowboy Space Corporation overcomes these challenges by enabling direct, on-demand, secure, and scalable energy distribution and data processing from space. This will revolutionize how we operate in orbit and on Earth, supporting the rapidly expanding space industrial base, ISAM (In-Space Servicing, Assembly, and Manufacturing) operations, remote regions, and military bases. Baiju Bhatt founded Cowboy Space Corporation in 2024. Inspired by his father’s work with NASA Langley Research Center, Baiju earned his B.S. in Physics and M.S. in Mathematics at Stanford before co-founding Robinhood, now a public company that has helped over 20 million Americans access the financial system. Cowboy Space Corporation has raised ~$365 million from Index Ventures, Interlagos, Construct Ventures, Breakthrough Energy Ventures, Andreessen Horowitz, NEA, and others. About the Role FPGA/RTL Engineer We’re looking for an experienced FPGA/RTL engineer to help build our state‑of‑the‑art optical communication system — the hard‑real‑time logic that connects optical communication terminals to embedded computers. You’ll work closely with our optical communication team to design and own HDL for optical‑link interfaces and high‑speed data pipelines for in‑orbit and ground communications. This is active development on a live flight program with near‑term launch milestones: you’ll join a small team, take full ownership of workstreams from day one, and see your designs fly. Responsibilities Design, implement, and verify HDL/RTL in SystemVerilog/Verilog for the FPGA subsystems of our state‑of‑the‑art optical communication system, from architecture through on‑orbit operation Partner directly with the optical communication team to design and implement FPGA logic for free‑space optical communication links, including modem interfacing, framing/synchronization, and high‑throughput data pipelines Develop high‑throughput communication pipelines for moving compute and optical‑link data from orbit to the ground, including high‑speed Ethernet (10/25/40/100GbE) MAC/PCS logic, SERDES/transceiver configuration, and link‑layer framing within the FPGA fabric Build memory‑mapped register interfaces (AXI) between FPGA logic and onboard flight software, and define the hardware/software contract with flight software engineers Own timing closure, synthesis, and implementation across Zynq UltraScale+ and Versal targets using Vivado and related toolchains Develop testbenches and simulation environments to verify designs before hardware, and validate on the bench with logic analyzers, oscilloscopes, and protocol analyzers Lead board bring‑up and hardware integration for new payload avionics, working closely with electrical and embedded software engineers Investigate anomalies spanning the optical‑link‑to‑ground and software chain, perform root cause analysis, and drive fixes across hardware/firmware/software boundaries Document designs and interfaces, and pair with teammates to spread ownership of the FPGA function across the team Basic Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in FPGA/HDL design, including architecture, verification, synthesis, and timing closure Proficiency in SystemVerilog or Verilog for production FPGA development Hands‑on experience with Xilinx/AMD FPGA platforms (e.g., Zynq, Zynq UltraScale+) and toolchains (Vivado, Vitis) Experience designing high‑speed digital interfaces and DDR/DMA‑based datapaths Experience integrating FPGA logic with embedded software, including memory‑mapped register interfaces and driver‑level debugging Experience developing FPGA platforms for multi‑gigabit data pipelines, including integrating forward error correction and other stabilization techniques — optical communication or high‑speed Ethernet experience strongly preferred Hands‑on hardware bring‑up and lab debugging experience with oscilloscopes, logic analyzers, and embedded debug tools Demonstrated ability to own open‑ended design problems independently and carry them from architecture through hardware and on‑orbit operation Preferred Qualifications Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline Experience in aerospace, defense, semiconductor, or other high‑reliability development Experience with free‑space or fiber optical communication systems — optical communication terminals, coherent/direct‑detection modems, or high‑speed optical transceivers Experience implementing Ethernet or other high‑speed serial protocol layers (MAC/PCS/PMA) directly in FPGA fabric — a big plus Understanding of network topology and architecture (routing, switching, protocol stacks) — a bonus Familiarity with Versal ACAP architecture and Quartus toolflows Experience with simulation and verification tools such as Questa/ModelSim, Xcelium, or Verilator, and with UVM or other structured verification methodologies Proficiency with C/C++, Python, and TCL for bring‑up, test automation, and tooling Experience with hardware‑in‑the‑loop testing and automated regression of FPGA designs Familiarity with fault‑tolerant design and radiation effects mitigation (SEU scrubbing, TMR, configuration memory integrity) for space applications Experience thriving in fast‑paced, high‑ownership environments with rapid iteration cycles Compensation and Benefits The salary range for this position is $150,000 – $200,000 annually. The actual base salary offered will depend on factors such as job‑related skills, experience, qualifications, and internal equity. Equity in Cowboy Space Corp. Employees and their eligible dependents may enroll in medical, dental, and vision insurance 401(k) retirement savings plan Paid time off 10 paid holidays per calendar year Paid parental leave Relocation assistance if applicable Daily lunch in the office and a fully stocked kitchen with beverages and snacks ITAR Requirements Export Control Requirement: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here . Disclaimer This job description is a summary of the primary duties and responsibilities of the job and position. It is not intended to be a comprehensive or all‑inclusive listing of duties and responsibilities. Contents are subject to change at Cowboy Space Corp.’s discretion. Cowboy Space Corp. is an equal employment opportunity employer. We consider individuals for employment or promotion according to their skills, abilities and experience. Cowboy Space Corp. is committed to complying with all applicable laws prohibiting discrimination based on race, color, religious creed, age, national origin, ancestry, physical, mental or developmental disability, sex (which includes pregnancy, childbirth, breastfeeding and medical conditions relating to pregnancy, childbirth or breastfeeding), veteran status, military status, marital or registered domestic partnership status, medical condition (including cancer or genetic characteristics), genetic information, gender, gender identity, gender expression, sexual orientation, as well as any other category protected by federal, state or local laws. #J-18808-Ljbffr