Senior/Staff Front-End Engineer (RISC Processor Integration)

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

We are seeking an experienced SoC Design Engineer to develop next-generation System-on-Chip (SoC) solutions. The ideal candidate will have hands-on experience implementing RISC processors (e.g., RISC-V or Arm), including processor configuration, subsystem integration, memory architecture, interconnects, and system bring-up.

• Configure and integrate RISC processor IP (RISC-V or Arm) into SoC platforms.


• Customize processor features, including cache configuration, MMU/MPU, PMP, debug, interrupt controller, and privilege modes.


• Integrate processor subsystems with:


• AXI/AHB/APB interconnects


• Interrupt controller (PLIC/GIC/NVIC)


• Develop RTL integration logic, wrappers, and system glue logic.


• Collaborate with verification teams to develop test plans and debug simulation issues.


• Work with firmware and software teams to enable bootloader, BSP, and operating system bring-up.


• Analyze and resolve system-level performance, power, and integration issues.


• Review third-party IP documentation and coordinate IP integration.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in SoC design, processor integration, or related semiconductor development.
• Strong experience integrating RISC processors, particularly RISC-V, into complex SoC platforms.
• Solid understanding of processor architecture, including:
• Pipeline architecture
• Cache hierarchy
• MMU/MPU/PMP
• Interrupt and exception handling
• Debug architecture
• Experience with AMBA bus protocols (AXI4, AHB, APB).
• Strong RTL design skills using Verilog/SystemVerilog.
• Experience with RTL development flows, including synthesis, lint, CDC analysis, and RTL quality checks.
• Familiarity with SoC boot flow and firmware interaction.
• Experience with simulation and debugging tools such as VCS, Xcelium, Questa, Verdi, or equivalent.
• Good understanding of clock/reset architecture and low-power design concepts.
• Strong system-level debugging, problem-solving, and communication skills.
• Ability to independently drive processor integration activities and collaborate with cross-functional teams.
• Experience working with third-party IP vendors and translating architecture specifications into implementation plans.
• Preferred Qualifications:
• Experience with commercial RISC-V cores (e.g., SiFive, Andes, Codasip) or open-source cores (e.g., CVA6, Ibex, CV32E40P).
• Familiarity with TrustZone, secure boot, or hardware security features.
• Experience in one or more of the following areas:
• RISC-V customization and configuration
• Cache coherence and coherent interconnects
• NoC integration
• DMA architecture
• JTAG / Debug Module integration
• FPGA emulation
• Performance analysis and optimization
• Multi-core SoC architecture
• AI or accelerator integration

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.