Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Job TitleQualcomm Technologies, Inc. is seeking a hardware micro-architect and RTL designer for its ASICS Engineering team.General SummaryAt Qualcomm, we believe in the power of technology. For decades, our innovations have transformed entire industries, improved billions of lives, and addressed many of society's biggest challenges. With the world becoming increasingly connected, we have a tremendous opportunity to shape a better future. As an R&D engine that has revolutionized the way people connect, our approach to innovation is strategic and purposeful. We understand that the success of our business is fundamentally connected to the well-being of our world.Our TeamOur mission is to ship the very best System-On-A-Chip products in the world, putting Qualcomm in a position of leadership, in all its businesses. We are looking for hardware micro-architects and RTL designers to develop SOC Interconnects, Cache and Memory Controllers for Qualcomm Snapdragon platforms across the best of the smartphones, the performance of Windows PCs and Chromebooks, virtual reality and augmented reality devices, and automotive solutions.What You Will Be DoingThe responsibilities include:Micro-architect, design and validate RTL for blocks and modules of SOC Interconnects, Interconnect Caches and memory subsystems, and power and system level designIdentify advanced ways to optimize hardware design for better performance, power, and costEvaluate the hardware feasibilities of complex algorithms and requirementsDevelop micro architecture and specification of the new generation designDevelop RTL for the corresponding micro architectureProvide essential verification and debugging activities for the corresponding design throughout the entire project cyclesOptimize the silicon cost and improve clock speedTroubleshoot silicon issues with products relevant to the corresponding designKey-QualificationsThe team is looking for candidates with:3+ years of experienceExperience or course work in Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, coverage-based design verificationExperience or course work in Computer Architecture, Computer Arithmetic, Low power design, C/C++/Python programming languages is desired.Experience or course work in designing RTL for CPU, cache controller blocks in ASIC is a plus!Good communication skill and desire to work as a team playerQualifications* Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5 OR * Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5 OR * PhD in Computer Engineering, Computer Science, Electrical Engineering, or related fieldPrior experience in ASIC Design and DV is a plus.Minimum Qualifications• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Pay Range and Other Compensation & Benefits$145,600.00 - $218,400.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.