Wireless ASIC Verification Engineer (UVM, Verilog)
Amazon Kuiper Manufacturing Enterprises LLC
A leading technology firm in Austin, Texas, is seeking a skilled engineer to join Project Kuiper. In this role, you will implement a verification environment and participate in validation processes and system-level verification using UVM. The ideal candidate possesses a Bachelor's degree in Electrical / Communications Engineering or Computer Science, along with a minimum of 2 years of experience in verification and UVM. This position offers a unique opportunity to contribute to groundbreaking satellite communication technology. #J-18808-Ljbffr Amazon Kuiper Manufacturing Enterprises LLC
- ...The MSIP UMC team is looking for an ASIC Design Verification Engineer to join our growing team. We develop... ...random and directed) using SystemVerilog/UVM/SystemC. Triage and debug regressions... ...random verification. Proficiency in Verilog, SystemVerilog, C/C++, UVM, OOP, and...Suggested
- ...India and 250+ in the US. Clear visibility to senior management supports constant professional growth. Job Description Strong System Verilog UVM, VMM, OVM experience Creating test bench CPU Memory Subsystem, ARM experience a plus All your information will be kept...Suggested
$114k - $170k
...Category Engineering Hire Type Employee Job ID 15246 Base Salary... ...machines. We lead in chip design, verification, and IP integration,... ...experienced and highly skilled ASIC Digital Verification Engineer... ...testbenches using SystemVerilog and UVM. Collaborating with design...SuggestedRemote work- ...Job Title Senior Verification Engineer Location Austin Role Summary We develop best‑in‑class digital... ...and scoreboards, and leverage advanced UVM VIPs Develop directed and constrained‑random... ...(CHI, ACE, AXI) Strong expertise in Verilog, SystemVerilog (VHDL is a plus)...SuggestedLocal area
- ...Overview Position: Design Verification Engineer (Einfochips) Location: Austin, TX and San Jose, CA What candidate will... ...At-least 6+ years of experience in System Verilog HVL and C/C++ At-least 6+ year of experience in UVM Experience in complete verification cycle which...SuggestedFull timeTemporary workWork at officeRemote work
- ...frequency trading companies in the world to find a verification engineer to help verify their complex low‑latency FPGA... ...functional verification experience for FPGA or ASIC designs. Hands‑on expertise in SystemVerilog and UVM, including stimulus development and code/...
- ...regulators. Design SystemVerilog/Verilog testbenches, checkers, and verification flows for system-level control... ...assertions, checkers, coverage, or UVM-based flows. Familiarity with power... ...~ B.S./M.S. in Electrical Engineering, Computer Engineering, or a related...Local areaRemote workFlexible hours
$125 - $135 per hour
...Professional Job Description: We are seeking a highly skilled Design Verification Engineer to join our team. The successful candidate will be... ...verification testbenches using languages such as System Verilog, UVM, and C++ to verify GPU functionality, performance, and...Contract work$120k - $225k
...Description We’re hiring experienced Design Verification Engineers from junior to senior levels to play a... ...development and execution using UVM or other advanced DV methodologies.... ...computer architecture. ~ Understanding of Verilog, SystemVerilog, and UVM. ~ Proven track...$147.4k - $272.1k
...innovative and key projects that Apple’s Silicon Engineering Group has embarked upon to date. As part... ...DV environments, craft highly reusable UVM TB, implement effective coverage-driven... ..., outstanding DV methodology, verification on accelerated platforms, knowledge of Cellular...RelocationFlexible hours- ...-edge solutions across AI, IoT, and HPC. Responsibilities / Requirements Senior Verification Engineer with 10+ years of experience Strong experience in VLSI verification Proficiency in UVM and SystemVerilog Hands-on experience across at least two full block or system verification...Full time
- ...looking for a Senior Front End (DV focused) Engineer to join a global team of Application... ...integration Proficiency in: SystemVerilog / UVM Advanced Testbench architecture... ...manufacturing test Knowledge of CDC/RDC, formal verification, and low-power flows Good understanding...Work at office
- ...Experience Architected and developed complex verification environments in SystemVerilog, including... ...components in SystemVerilog and UVM along with formal to achieve verification of the design. Coordinate with RTL engineers to implement logic design for better clock...
- ...SoC Design Verification, SystemVerilog, UVM, Object-Oriented Programming, Python, C++, Java, Digital Design, Computer Architecture, Networking Protocol... ...most innovative and key projects thatApple’s Silicon Engineering Group has embarked upon to date. As part of ourteam, you...Flexible hours
- ...Senior Firmware Verification Engineer Job Description Renesas Electronics America is seeking a mid-level PMIC Firmware Verification Engineer to... ...verbal communication. Preferred Qualifications Experience with UVM or other structured verification methodologies. Familiarity...Work at officeLocal areaRemote workFlexible hours2 days per week
$200k - $320k
...Description About the role We're looking for a experienced Design Verification engineer with at least 5 years of pre-silicon verification experience... ...both hardware and software perspectives ~ Well-versed in UVM methodology and testbench architecture ~ Ability to define...H1bVisa sponsorshipWork visaFlexible hoursNight shift$62 per hour
...industry, is seeking a Silicon Validation Engineer to join their team. As a Silicon... ...electrical characterization of a small ASIC containing various IP blocks. Prepare for... ...Electrode Manufacturing Senior Validation and Verification (V&V) Engineer Sr. Manufacturing Process...Full timeInternshipRemote work- ...our team. We are looking to add a Verification Engineer II to our team. If you enjoy working in... ...data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB... ..., SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional...Permanent employmentFull timeContract workWork experience placementLocal area
- ...Job Description Job Description Analog/Mixed-Signal Verification Engineer focusing on high-performance analog-to-digital and digital-to-analog... ...digital behavioral modeling and familiarity with behavioral Verilog / Verilog-A code, including wreals ~ Familiar with Cadence...
- ...Get notified about new Senior Design Verification Engineer jobs in United States . Senior Design Verification and Methodology Engineer, Google... ...Senior Design Verification Engineer, HW Compute Group Senior ASIC Physical Design Engineer - Maynard, MA Senior System ASIC...Remote work
- ...devices. Together, you and your team will enable our customers to do all the things they love with their devices. The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU...
- ...We are looking for an experienced digital and mixed-signal verification engineer who excels working in large complex systems with and enjoys utilizing... ...verification Extensive digital verification background UVM expertise Verification (and ownership a plus) of RTL for...
- ...DDR6 and beyond. Job Description · Verification of DDR5 Data Buffer to meet functional... ...test on System-level and block level using UVM methodology. · Participate in... ...Technically work with a team of verification engineers, providing technical guidance and mentoring...Local areaRemote workFlexible hours
- ...Opening from Default - Austin, TX - No Sponsorship Available. At Cirrus Logic, mixed-signal engineering drives our company. We develop high-performance, low-power signal processing solutions in audio, voice and haptics, delivering innovative end-user experiences and solving...
- ...Duration: 12+ Months The Role Technical, hands-on engineer responsible for Datacenter Server product power management feature validation... ...but highly experienced team that led the power management verification and optimization of client's multi-generation server product....
$60 - $65 per hour
...based on your skills and experience — talk with your recruiter to learn more. Base pay range $60.00/hr - $65.00/hr Role: Validation Engineer Location: Austin, Texas – Onsite Seniority Level: Mid-Senior level Employment Type: Contract Job Function: Quality Assurance...Contract work- ...Manufacturing Engineer Are you looking for an exciting opportunity working for a Global Technology Leader? At Aviat Networks, we... ...Aviat Networks is the world's largest independent supplier of wireless transmission systems. We are recognized worldwide for cutting-edge...Contract workLocal areaWorldwide
$83k - $139k
...: The Brain Interfaces Mechanical Engineering team is responsible for the mechanical... ...microfabricated thin-film electrodes, wireless charger, and associated accessories. This... ...and electro-mechanical test systems for verification and validation of products ranging from...Full timeTemporary workFlexible hours- ...candidates. This company was founded by a trio of experienced engineers aiming to innovate underwater audio technology. Our client... ...built on FPGA technology -Create digital logic design using Verilog / SystemVerilog -Implement high-speed DSP algorithms in digital...Full timeContract work
$166k - $249k
...Category Engineering Hire Type Employee Job ID 17853 Base Salary Range $166000-$24900... ...learning machines. We lead in chip design, verification, and IP integration, empowering the... ...programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar languages). *...Remote work
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