Senior Analog / Mixed Signal Application Engineer

Aerospace, Defense & Government Senior Analog/Mixed Signal Application Engineer

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview

The Aerospace, Defense & Government Senior Analog/Mixed Signal Application Engineer specializing in Analog Mixed-Signal Design provides critical technical support to Intel Foundry Services customers on PDKs, design methodologies, and implementation flows. This role ensures successful customer tape-outs through expert guidance on analog/mixed-signal design challenges while driving quality improvements in design kits and documentation.

Key Responsibilities

• Provide comprehensive tool/flow/methodology support to address customer analog mixed-signal design issues and challenges, ensuring successful tape-outs and maximum customer satisfaction
• Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on AMS design and layout issue resolution
• Support customers through complex analog design challenges and advanced process technology adoption
• Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
• Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
• Develop best practice guidelines for analog mixed-signal design implementation across advanced CMOS processes
• Provide technical direction on custom/analog mixed-signal design and layout methodologies
• Support analog tool flows including schematic entry, analog/RF simulation, extraction, post-layout simulation, and reliability validation
• Drive methodology improvements to streamline customer design workflows and enhance design productivity

Core Competencies

• Self-driven and results-oriented with capability to effectively manage multiple tasks
• Strong analytical problem-solving skills for complex analog design challenges
• Effective communication skills with experience in collaboration, active listening, and providing constructive feedback

Qualifications:

• Minimum Qualifications
• US Citizenship required
• Ability to obtain US Government Security Clearance
• Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field of study
• 5+ years of experience with advanced CMOS processes (16nm and below)
• 4+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, shell scripting)
• Hands-on experience in Design Implementation and methodology, specifically in Custom/Analog Mixed-Signal design/layout
• Preferred Qualifications
• Active US Government Security Clearance with a minimum of Secret level.
• Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work.
• Hands-on experience with analog tool and flows: Schematic entry, analog/RF simulation, extraction, post layout simulation, reliability validation.
• Hands-on experience with custom layout of analog blocks and Layout migration b/w different advanced FINFET tech nodes.
• Experience in design of RF/analog/mixed-signal blocks: Low-noise amplifiers, filters, mixers, VCO, PLL, clock recovery, clock distribution, ADC / DAC, etc.
• Customer facing experience.
• Experience in SOTA Process technology (7nm and below) and PDK based technology evaluation.
• Experience with thermal analysis at the block and die level using tools such as Ansys Icepak and/or Cadence Celsius

What We Offer

• Opportunity to work with cutting-edge analog mixed-signal technologies for aerospace, defense, and government applications
• Direct customer engagement and technical leadership in advanced semiconductor design
• Access to Intel's most advanced foundry technologies and comprehensive analog design tool suites
• Competitive compensation
• Professional development in analog design methodologies and foundry services
• Direct impact on national security through advanced analog semiconductor solutions

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Arizona, Phoenix

Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro

Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.