Senior ASIC DFT & DV Engineer (DVE/Verdi)
Cisco Systems
Cisco’s Silicon One team seeks an experienced hardware test engineer to lead test planning and bench development for Design-for-Test architecture. You will collaborate across design, verification, and PD teams to validate test logic and enable robust in-system testing through post-silicon validation. The role requires strong SystemVerilog skills, DVE/Verdi debugging, and scripting in TCL/Python/Perl, with 7+ years of experience (or 4+ if MS) in EE. Hybrid role across San Jose or Austin. #J-18808-Ljbffr
Vacancy posted 3 days ago
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