Director, PD development and integration

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (


About the role:

We are seeking a highly skilled team member to lead the development and manufacturing transfer of high-speed silicon photodetectors (PDs) optimized for microLED-based multi-terabit-per-second communications. This role focuses on managing critical partnerships and processes to enable the successful development and transfer of photodetectors into high-volume manufacturing working with leading semiconductor fabrication partners. This position is based in Sunnyvale, California. This position starts with a single hire with a plan to grow the team as the company and product develops. This is an ideal opportunity for someone looking to develop into a senior engineering management position.


Responsibilities:

• New PD Design Development: Lead the development of innovative PD designs optimized for our applications. Work with internal and external resources to design and simulate PD performance. Work with internal resources to characterize PDs.

• Foundry Partnership Management: Lead and manage the foundry partnership, including the transfer of new photodetector designs and oversee any necessary process modifications. Ensure alignment between Avicena's technical and business requirements and the foundry partner's capabilities.

• Wafer Testing Management: Oversee the development and implementation of wafer testing strategies, including identifying and managing external vendors for wafer-level testing. Leverage expertise to define and validate test methodologies.

• Final Test Development: Collaborate with vendors to set up and manage final test processes, ensuring robust performance validation of packaged devices.

• Qualification: Work with a multi-disciplinary team to establish qualification of Avicena's manufacturing flows and ultimate qualification to industry standards.

Qualifications:

• Educational Background:

• • BS, MS, or PhD in Materials Science and Engineering, Electrical Engineering, or Applied Physics.

• Industry Experience:

• • Proven experience managing foundry partnerships or foundry processes.

• • Deep understanding of semiconductor device physics and characterization techniques (e.g., SIMS, XRD, SEM, TEM).

• • Familiarity with semiconductor wafer fabrication processes, including photolithography, thin-film deposition, and etching.

• • Experience with packaging technologies, including hybrid bonding and wafer stacking is a plus.

• • Ability to manage outsourcing to high volume manufacturing partners.

• Testing Expertise:

• • Ability to oversee high-speed optoelectronics testing, including wafer-level and final test processes.

• Project Management Skills:

• • Excellent interpersonal and communication skills to collaborate with internal teams, manage external vendors, and present complex technical findings.

• • Ability to manage timelines, overcome technical challenges, and drive solutions in a dynamic work environment.