Design for Test Engineer: DFT & ATPG Expert
ComTec Information Systems (IT)
ComTec Information Systems (IT) is seeking a Design for Test (DFT) Engineer for a 1-year hybrid assignment with travel to Santa Clara. The role requires 3+ years of DFT experience and hands-on work with Siemens Tessent DFT tools. Candidates should have strong DFT fundamentals, including controllability and observability, scan insertion, and ATPG/MBIST expertise. Proficiency in IO tests, clock DFT, and RTL (Verilog/SystemVerilog) is essential. #J-18808-Ljbffr ComTec Information Systems (IT)
Vacancy posted 1 day ago
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