ADCE Packaging Design Architect

Job Overview Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon‑package board performance and pinout. Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral in the product lifecycle management system of record. Responsibilities Conduct substrate fit and routing studies. Define substrate design rules and conduct reviews. Resolve DRCs to optimize package design. Document design decisions in the PLM system. Qualifications Ph.D. or master’s in electrical engineering, chemical engineering, mechanical engineering, or material science. 10+ years of in-depth experience in package design, PCB design, or IC digital design. Strong technical background in design and electrical analysis. Solid background in semiconductor fabrication and packaging. Strong analytical and problem‑solving skills. Ability to work independently at various levels of abstraction. Strong organization, time management, and communication skills. Proficiency with design and electromagnetic simulation tools such as Mentor, Cadence, SPICE, Ansys, etc. Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx). Experience and knowledge with assembly process, test, and characterization techniques preferred. Position of Trust This role is a Position of Trust requiring consent to and pass an extended background investigation. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance. #J-18808-Ljbffr Intel Corporation