Lead RTL Design Architect - NoC & High-Speed Interconnects

Architect Labs

Architect Labs is seeking a senior RTL Design Engineer to own the on-chip fabric and NoC architecture for production silicon. You will drive the end-to-end RTL flow from architecture through synthesis, ensuring timing closure and high-bandwidth, low-latency interconnects across the SoC. You will work closely with DV, SW, and ML teams to refine microarchitectural specs, implement AMBA-based fabrics, and enable FPGA prototyping for early validation of the interconnect stack. #J-18808-Ljbffr

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Vacancy posted 16 hours ago

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