Lead RTL Architect for AI Accelerator Silicon

DensityAI, Inc.

DensityAI, Inc. is seeking an experienced RTL design engineer to architect and implement digital blocks for its AI accelerator. You’ll translate microarchitecture specifications into synthesizable SystemVerilog RTL, own the datapath, interconnect, and control logic, and drive design quality from RTL to tapeout. You will collaborate with DV, PD, and DFT teams to ensure timing closures, power efficiency, and robust testability, leveraging scripting to streamline flows. #J-18808-Ljbffr

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Vacancy posted 5 days ago

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