Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Lead DFT Architect for Next-Gen AI Chips

SambaNova

SambaNova Systems is seeking a Principal Design for Test (DFT) Engineer to help build state-of-the-art RDU chips for ML/AI. You will own DFT architecture, verification, ATPG, MBIST and silicon bring-up for high-performance chips. Responsibilities include defining DFT for large SoCs, maintaining ATPG flows, automating DFT tasks, and integrating JTAG/IJTAG interfaces for test access. Collaboration with STA and PD teams is required to meet timing closure and yield goals. #J-18808-Ljbffr

Vacancy posted 3 days ago
Similar jobs that could be interesting for youBased on the Lead DFT Architect for Next-Gen AI Chips in San Jose, CA vacancy
  • $206.4k - $303.25k

     ...organization through the strategic application of AI. **Mission**Lead the AI transformation of hardware design...  ...and drive the company's AI strategy for chip design and to lead its deployment into...  ...directly with design, verification, DFT, implementation, and EDA tooling teams... 
    Suggested

    Altera Corporation

    San Jose, CA
    4 days ago
  •  ...owning multiple functional areas, developing reusable code, and debugging across ASIC, software, and hardware levels. The candidate will lead DV work, define new verification methodologies, and collaborate with ASIC and apps teams to resolve architectural issues, while... 
    Suggested

    Cisco

    San Jose, CA
    4 days ago
  • Eridu Corp., a Silicon Valley hardware startup, seeks a senior EE to define the DFT architecture for a multi-chip SOC, encompassing test design functions such as Scan, BIST, Memory Repair, and advanced DFT techniques. You will work with a world-class engineering team, require... 
    Suggested

    Eridu Corp.

    Saratoga, CA
    2 days ago
  • $195k - $250k

    Eridu, a Silicon Valley hardware startup, seeks an experienced engineer to define the DFT architecture for a multi-chip SOC, covering test design, SDC constraints, and ATPG. You will work with RTL and gate-level simulations and oversee high-coverage scan techniques, including... 
    Suggested

    Eridu Corporation

    Saratoga, CA
    1 day ago
  • $200k - $275k

     ...Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions...  ...LinkedIn and X.Principal AI Accelerator Architect Lead Boston, MA; San Jose, CA Team: MicroAI...  ..., computed, and executed within a chip under stringent power, latency, and reliability... 
    Suggested
    Permanent employment
    Full time
    Work at office
    Day shift

    Analog Devices

    San Jose, CA
    7 days ago
  •  ...AMD's Circuit Technology team seeks an experienced DFT/DFx Lead to drive methodology and RTL execution for high-speed SerDes and memory IPs. You will own architecture definition, RTL implementation, and test strategies across design, verification, CAD, and test engineering... 

    Advanced Micro Devices , Inc.

    Santa Clara, CA
    11 hours ago
  •  ...Cisco Systems, Inc. in San Jose seeks a DFT Verification Lead to drive test planning and bench development for robust DFT architectures. You will work with Front-end RTL and backend PD teams to validate test logic across implementation and post-silicon flows, with mentorship... 

    Cisco

    San Jose, CA
    2 days ago
  •  ...seasoned SoC Design Verification Lead to architect and drive verification strategy for next-generation semiconductor products...  ...teams, applying formal methods, SVA, AI-driven techniques, and advanced...  ...complex blocks, subsystems, and full-chip fabrics. #J-18808-Ljbffr

    TYLsemi

    San Jose, CA
    13 hours ago
  •  ...discovery to powering AI and the technologies people...  ...you’re designing next-gen processors, enabling AI...  ...breakthroughs, or bringing leading edge products to market...  ...career.THE ROLE:As a DFT Architect you will drive DFT architecture...  ...implementing complex chip-level DFT... 

    AMD

    San Jose, CA
    5 days ago
  • $209.5k - $295k

     ...technical leader to drive the next generation of AI-powered semiconductor design solutions. This role will lead the development of Agentic...  ...times, and advance autonomous chip design capabilities. Key...  ..., Software & Infrastructure Architect Enterprise-scale AI and... 
    Local area
    Shift work

    Altera

    San Jose, CA
    8 hours ago
  • GlobalFoundries is seeking a SiPh Technology Architect to drive R&D projects for next‑gen SiPh solutions focused on data center applications, with potential automotive and biomedical applications. Deep expertise in device physics, design, simulations, and materials integration... 

    GlobalFoundries

    Santa Clara, CA
    4 days ago
  •  ...CA to partner with global engineering teams and optimize the full chip design workflow from inception to production. You will build...  ...drive data‑driven decisions, reduce cycle times, and contribute to next‑generation chip development in a #J-18808-Ljbffr NVIDIA Corporation

    NVIDIA Corporation

    Santa Clara, CA
    4 days ago
  •  ...HYPERLUME in San Jose, CA, seeks a Senior Director, AI Interface Architecture to own interconnection architecture linking XPUs across node, rack, and cluster scales so that large-scale LLM training and inference run efficiently. The role focuses on scalable AI systems... 

    ArcTern Ventures

    San Jose, CA
    4 days ago
  •  ...d-Matrix inc. is seeking a Principal Architect specializing in Performance Analysis and Modeling to join our Santa Clara, CA team. The role involves analyzing ML workloads, developing hardware/software features, and creating analytical models that enhance performance across... 

    d-Matrix inc.

    Santa Clara, CA
    4 days ago
  •  ...Inc. is seeking an experienced RTL design engineer to architect and implement digital blocks for its AI accelerator. You’ll translate microarchitecture specifications...  ...RTL to tapeout. You will collaborate with DV, PD, and DFT teams to ensure timing closures, power efficiency, and... 

    DensityAI, Inc.

    Mountain View, CA
    4 days ago
  •  ...Arm is seeking a Lead Architect in California to drive the definition and exploration of next‑generation system architectures across data center and networking domains. You will align market trends, hyperscaler needs, and software ecosystems with Arm’s infrastructure... 

    ARM

    San Jose, CA
    3 days ago
  •  ...Graphcore in Milpitas, California, seeks a Principal Storage Architect to define high-performance storage architecture for AI training and inference workloads. You will lead the design of local and distributed storage tiers, optimize data paths among CPUs, accelerators... 
    Local area

    Applied Methods Inc

    Milpitas, CA
    9 hours ago
  •  ...seeks a Principal Physics Algorithms Engineer to define and develop next-generation physics-based technologies for e-beam semiconductor...  ...influence multiple engineering groups, partner with CV/ML teams to embed physics in AI-driven solutions, and mentor junior #J-18808-Ljbffr

    ASML

    San Jose, CA
    2 days ago
  •  ...LTIMindtree is seeking a ServiceNow Technical Architect in Santa Clara, CA, with remote options. You will lead architecture reviews, advise on platform roadmaps, and...  ...environments to drive customer value. You will guide AI capabilities such as Now Assist and AI Agents,... 
    Remote work

    LTM

    Santa Clara, CA
    5 days ago
  •  ...BMC Software, Inc. is seeking a senior AI leader to design and build enterprise-grade agentic AI systems. You will guide multi‑agent orchestration, integrate with APIs, and drive RAG solutions using vector databases. Ideal candidates have extensive experience with LLMs... 

    BMC Software

    Santa Clara, CA
    5 days ago
  • $144k - $329.1k

     ...wherever you want it to go. Join EY and help to build a better working world. The opportunity We’re hiring an experienced Lead AI Software Architect that to lead a team of domain architect experts in designing and implementing AI Agent Control. This role is for a... 
    Summer holiday
    Flexible hours

    EY

    San Jose, CA
    3 days ago
  •  ...Engineer in Santa Clara with remote options to define and build AI-enabled automation across the software lifecycle. You will own the...  ...auditable guardrails while shipping high-impact automations. You'll lead hands-on work on a kernel compiler, firmware, device drivers, and... 
    Remote job

    d-Matrix

    Santa Clara, CA
    3 days ago
  • Oso Semiconductor Inc. in Mountain View, CA, is seeking a Principal RFIC Design Engineer - Chip Lead to own top-level integration of our next-generation multi-channel beamformer ICs. You’ll drive chip architecture, floorplanning, block integration, RF/analog performance... 

    Oso Semiconductor Inc.

    Mountain View, CA
    1 day ago
  • Advanced Micro Devices, Inc. (AMD) seeks an AI/ML Project Lead to drive production-quality AI solutions for DFX design and verification. You will partner with DFT, DFD, CAD, design and software teams to translate engineering knowledge into deployable AI capabilities and... 

    Advanced Micro Devices, Inc.

    Santa Clara, CA
    2 days ago
  •  ...Persimmons, Inc. is building AI hardware infrastructure and seeks a founding Senior ASIC Design Verification Engineer to own the verification...  ...and is free of critical bugs before tape-out. You will lead test plan development, build portable UVM testbenches, drive... 
    Flexible hours

    Persimmons, Inc.

    San Jose, CA
    2 days ago
  •  ...Micron Technology is seeking a senior technical lead in packaging pathfinding for next generation memory systems, spanning from data centers to edge-AI. You will guide long-term package technology directions and partner with customers to turn ideas into scalable products... 

    Micron Technology

    San Jose, CA
    4 days ago
  •  ...Senior Emulation Engineer to own and scale the emulation infrastructure for its next-generation Physical AI SoC. You will set up flows on Palladium, Veloce, and Zebu and partner with architects, RTL, verification, and software teams to accelerate pre-silicon validation.... 

    Velaura

    Santa Clara, CA
    4 days ago
  •  ...welcome highly talented Physical Design Architects and Chip Leads to join our Cadence Performance...  ...system (ADAS) automotive and physical AI, and cutting-edge artificial intelligence...  ...internal stakeholders, including RTL, DFT, CAD, and Library teams.Preferred QualificationsMaster... 
    Full time

    Cadence Design Systems

    San Jose, CA
    7 days ago
  •  ...KLA is seeking a Senior HPC Platform Architect in Milpitas, CA to design and lead next-generation HPC platforms for semiconductor manufacturing and AI workloads. You will define architecture across software, hardware, networking, storage, GPU acceleration, and cloud integration... 

    KLA

    Milpitas, CA
    2 days ago
  •  ...Etched is building a new category of AI hardware in San Jose, focused on frontier inference clusters. As a Physical Design Methodology Engineer, you will own the PD flow from first principles, creating infrastructure that lets design teams iterate rapidly and yield strong... 

    The Consensus

    San Jose, CA
    3 days ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Lead DFT Architect for Next-Gen AI Chips. Be the first to apply!