Senior IC Package Design Engineer

Fully Onsite in the San Francisco Bay area or Orange County Ca Open to a Senior or Mid level Engineer $300-450K Total Compensation Plan- Base, Bonus, Stock (depends on skillset/experience level) We’re partnering with a leading semiconductor organization developing next‑generation integrated circuits on advanced silicon nodes (7nm, 5nm, 3nm and smaller). This is a critical cross‑functional role at the intersection of chip design, system architecture, SI/PI, thermal, and manufacturing—owning packaging solutions from concept through high‑volume production. What You’ll Do Co‑design package architecture with chip, IP, and PHY teams (high‑speed SerDes, PCIe, data converters), including die floor planning, bump architecture, and IO placement Optimize package stack‑ups, layer counts, routing, BGA patterns, and power integrity to meet system, performance, and manufacturing requirements Execute advanced substrate and package designs using Cadence APD (or equivalent), ensuring SI/PI, thermal, mechanical, and reliability targets are met Define assembly BOMs, process flows, design rules, and package PORs for advanced silicon nodes Lead package development, qualification, and deployment through NPI and HVM Drive collaboration with OSATs, substrate suppliers, and manufacturing partners Provide sustaining support in production, including issue resolution, yield, reliability, and multi‑source enablement Required Background BS/MS/PhD in EE (preferred), ME, Materials Science, or related field 7+ years of hands‑on experience in advanced IC packaging for leading‑edge nodes Substrate design and flip‑chip BGA technologies SI/PI principles and high‑speed IO packaging Proficiency with Cadence Allegro APD / SIP or comparable tools Experience working with global OSATs and substrate vendors Proven ability to drive programs from architecture through HVM Strong communication and cross‑functional leadership skills #J-18808-Ljbffr Fidelis Companies