Design Verification Engineer
Keylent Inc
Design Verification Engineer
Design Verification Engineer (8-15 Years Experience)
Work Location – Folsom, CA USA (1st Day onsite)
Max Salary Pay is 130 -150K -Only Full Time
Number of positions – 4
Key Responsibilities:
- Utilize hands-on experience in SystemVerilog, UVM, and Testbench development to facilitate the verification process.
- Perform thorough debugging and troubleshooting to identify and resolve issues efficiently.
- Conduct full-chip and SoC simulations to validate design functionality and performance.
- Demonstrate expertise in subsystem verification, encompassing controllers and PHY components.
- Verify bus interfaces, controllers, and PHYs to guarantee seamless integration and functionality.
- Ideally, possess experience with subsystems/IPs such as DDR5, LPDDR, PCIe, Ethernet, UCIe.
Vacancy posted 1 day ago
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