Senior Static Timing & Signoff Engineer for Low-Power SoCs
Silicon Laboratories Inc.
Silicon Labs in Austin, TX is seeking a Senior Static Timing Analysis Engineer to develop constraints and signoff for low‑power Wireless SoCs. You will work with multi‑core IPs and complex clock networks to meet power targets and performance goals. You will collaborate with global teams, evolve flows, and contribute to timing closure across SoC integration and IP. A strong background in Verilog/SystemVerilog and scripting is essential. #J-18808-Ljbffr Silicon Laboratories Inc.
Vacancy posted 2 days ago
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