Senior ASIC Verification Engineer - DDR Memory IP
Synopsys
Synopsys Inc. is seeking an experienced verification engineer to lead DDR PHY and memory subsystem IP verification. You will translate architectures into executable tests, build scalable UVM testbenches, write assertions, and drive coverage to catch protocol violations before tape-out. You will mentor junior engineers, collaborate with design teams, and integrate AI-assisted verification tools into our workflow, enabling faster, more robust silicon validation across product families. #J-18808-Ljbffr
Vacancy posted 5 days ago
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