Design Verification Engineer
Experis
Verification Engineer
Projected 12-month contract. Work remotely within the U.S. only.
As a Verification Engineer in the Accelnet Hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array (FPGA) SmartNICs (Azure Boost) in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, improving network security, enhancing connection establishment performance, and improving performance with Remote Direct Memory Access (RDMA) and custom network protocols.
- Deliver verification plans and test cases for assigned features on schedule.
- Achieve verification closure through comprehensive coverage tracking, including functional, code, assertion, and test plan coverage.
- Develop and execute high-quality directed, random, and stress tests that validate feature functionality and corner-case scenarios.
- Identify and drive resolution of critical design, integration, and performance bugs before milestone release.
- Enhance verification environments by adding reusable testbench components, checkers, scoreboards, assertions, and automation.
- Improve overall verification quality by introducing stress, backpressure, congestion, error-injection, and recovery scenarios.
- Demonstrate strong ownership in regression debugging, root-cause analysis, and bug triage.
Vacancy posted 5 days ago
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