Design Verification Engineering

If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Design Verification EngineerBroadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments.The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.Requirements:12+ years of experience with verification concepts and architectures for complex digital and MXS circuitsExperience verifying designs at the block and system levels.Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuitsExperience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)Experience with Synopsys, Cadence, and Mentor simulations toolsDemonstrated ability to plan and deploy complex, reusable, and scalable verification environmentsExperience with Perl/Python and Tcl or other scripting languagesExperience with version control systems (DesignSync, git)Superior writing, grammar, and verbal communication skillsExcellent problem solver; develops and employs automated processes where applicableWorked independently and in a global team and dynamic environment in a highly visible rolePossesses ability to learn and adapt to new tools and methodologies on the flyMust have legal authorization to work in the USIt is a plus if the candidate has expertise in one or more of the following areas:Experience with hardware design and debugExperience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platformsFormal verification concepts / experience is a plusExperience with verifying iJTAG network using ICL and PDL in the Tessent tool a plusExperience with co-simulation a plusEducation and Experience required:BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.Compensation and BenefitsThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.USA-CA Irvine Alton Parkway Bldg 1Type: Full time