Design Engineering S

Overview ASIC RTL Design Engineer at Ericsson. Hybrid work schedule, non‑remote.

We develop custom silicon for 5G networks that power global connectivity infrastructure. The engineering team designs, verifies, and delivers functional RTL blocks that become part of ASICs.

Use state‑of‑the‑art EDA tools to design and verify complex ASICs.

Collaborate with the backend team to close on synthesis, area, and timing.

Qualifications BS in Electrical or Computer Engineering.

Several years of industry RTL design experience at block and/or top level.

Solid foundation in digital logic design.

Strong command of C/C++, TCL, and/or Python.

Deep understanding of clock domain crossing (CDC) and static timing analysis (STA).

Bonus points for: experience with AMBA interfaces (APB, AXI, ACE‑Lite, CHI), background in computer architecture or VLSI systems, IP knowledge across SerDes, PCIe, ARM subsystems, DSPs, accelerators, or Ethernet, experience with Cadence, Mentor, or Synopsys toolchains, and comfort with Git and Linux environments.

Salary is competitive and based on location, experience, and performance.

Short‑Term Variable Compensation Plan and annual bonus opportunities, comprehensive medical, dental, vision, and disability coverage.

401(k) plan with company match, insurance credits, employee stock purchase plan, paid vacation, maternity leave, and parental or adoption leave.

Accommodation Contact To request an accommodation due to a disability, email hr.direct.