Architect- Architecture Design

PMIC Architect

San Jose, California, United States

About this position

As Power Architecture Lead for PMIC, you will own the IVR architecture end-to-end – power conversion topology, digital control engine, and analog subsystems.

You will work directly with the Head of Engineering, digital architecture leads, and analog design team, and engage foundry partners and key customers at the architecture level.

This role requires equal fluency in power electronics and mixed-signal IC design. You will define the architecture, validate trade‑offs across topology, packaging, and thermal constraints, and drive execution through tape‑out.

Key Responsibilities

Define IVR architecture: multi‑phase interleaved buck converter topology, phase count configurability, switching frequency selection, and efficiency targets across load conditions

Architect the digital control engine: per‑phase duty cycle control, current balance, DVFS sequencing, and transient response optimization for AI workload dynamics

Define the control and telemetry interface

Establish power domain architecture for multi‑domain compute targets: phase allocation, rail sequencing, and cross‑domain coordination

Define input power spec, inrush management, and integration requirements for in‑package passive components including integrated inductors

Define requirements for analog subsystems: gate drivers, current sensing (DCR / integrated sense), on‑chip thermal diodes, and oscillator / clock generation

Oversee integrated inductor evaluation and selection – saturation current, DCR, Q‑factor, and co‑design with converter switching frequency

Establish PVT corner strategy and margin targets across process, voltage, and temperature for all analog blocks

Drive analog‑digital co‑design: ensure digital control loop stability across all PVT corners with defined phase margin and gain margin targets

Define ESD and latch‑up protection strategy for high‑current power bumps

Guide process node selection for Gen 1 and roadmap generations – evaluate trade‑offs between power density, analog capability, and cost

Lead IP evaluation for gate driver, ADC, and reference blocks; define custom vs. licensed IP strategy

Drive DFT strategy for power chiplet: stuck‑at fault coverage, analog BIST for converter calibration, and production test requirements

Translate AI compute platform power delivery requirements into product specifications – engage customers at the architecture level to validate rail counts, current targets, and transient profiles

Interface with foundry partners on process capability, passive integration options, and packaging design rules

Support technical due diligence for strategic partnerships and customer evaluations

Define packaging integration requirements

Define the multi‑generation architecture roadmap – establish a clear migration path from initial process node to advanced nodes with improved power density and packaging integration

Required Qualifications

15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC‑focused semiconductor environment

Deep expertise in multi‑phase synchronous buck converter design – topology selection, loop compensation, stability analysis, and efficiency optimization across load

Mixed‑signal IC design fluency: gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes

Hands‑on experience with integrated passive components – on‑chip or in‑package inductors, capacitors, and their interaction with converter performance

Advanced packaging familiarity: flip‑chip, 2.5D/3D integration, bump map design, and thermal/electrical co‑design for power‑dense applications

Experience driving power IC tape‑outs from architecture definition through silicon bring‑up and characterization

Proficiency in power converter simulation: SPICE‑level transient analysis, AC loop stability, and PVT corner sweeps

Preferred Qualifications

Experience with kilowatt‑class power delivery for AI accelerators, GPUs, or high‑performance CPUs

Familiarity with in‑package voltage regulator architectures (FIVR, LEGO‑style VR, or substrate‑embedded passives)

Background in PMBus / I2C / proprietary digital power management interfaces – experience migrating from legacy interfaces to die‑to‑die control fabric

Prior startup experience or comfort with early‑stage technical ambiguity and fast‑paced execution

Pay Range

The pay range for this role is: 175,000 – 350,000 USD per year (San Jose (HQ))

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