Toolmaker -- Full-Time

At Intel, Design Technology Platforms (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DTP cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs.The Technical Lead position within the Design Enablement (DTP) organization of Intel Foundry is a Design Enablement Applications and Support Technical Lead position chartered to lead a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test chips when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions.Lead and develop a high-performing engineering team by setting priorities, driving execution across organizational boundaries, and fostering an inclusive and collaborative work environment. Provide technical leadership, mentoring, and coaching while ensuring delivery of engineering objectives aligned with schedule, quality, and cost targets.Direct and coordinate engineering activities, allocate resources effectively, and drive problem resolution through sound technical judgment. Promote team values, accountability, and continuous improvement while guiding employee development, performance, and productivity. Required behavior traitsStrong customer focus with a commitment to responsive support and issue resolution.Minimum Qualifications:BS degree with 10+ years of experience or MS degree with 8+ years of experience or PhD degree with 6+ years of experience in Electrical Engineer or Computer Engineering or related field.Industry direct experience and in-depth knowledge to support customers in ASIC/Physical Design and/or Physical Verification/runsets, in advanced technology nodes, or EDA tools.Preferred Qualifications Experience in advanced-node semiconductor design and verification methodologies.Experience with customers and stakeholders to resolve complex design and technology challenges.Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.US, Arizona, PhoenixType: Full time