Technology / Innovation Architect

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

Altera is seeking an accomplished Memory Validation Architect to define and lead the validation architecture for next-generation memory subsystems across our FPGA portfolio. This is a highly visible technical leadership role responsible for shaping the validation strategy for DDR5, LPDDR5/LPDDR6, HBM, and future memory technologies from architecture definition through production.

The ideal candidate is a recognized industry expert with deep experience in memory controller and PHY architectures, post-silicon validation, system architecture, silicon debug, and customer enablement. You will partner closely with architecture, RTL, firmware, board design, signal integrity, software, product engineering, and key memory vendors to ensure industry-leading quality, performance, interoperability, and customer success.

Beyond execution, you will define scalable validation methodologies, influence product architecture, mentor engineering teams, and establish best practices that span multiple FPGA generations.

Define and own the end-to-end validation architecture and strategy for memory subsystems across multiple FPGA product families.

Drive validation planning from architecture definition through silicon bring-up, product qualification, and customer deployment.

Training and calibration algorithms

Performance characterization

Stress testing

Establish silicon characterization methodologies including voltage, temperature, frequency, process variation, and manufacturing margin analysis.

Lead complex root-cause investigations involving RTL, firmware, board design, signal integrity, package interactions, and system software.

Drive architecture improvements by identifying validation gaps and influencing future memory subsystem designs.

Define customer validation strategies and drive rapid resolution of customer-reported issues.

Establish metrics and dashboards that measure validation coverage, product quality, debug efficiency, and execution readiness.

A passion for building scalable validation methodologies and world-class engineering practices.

Strong communication skills with the ability to collaborate effectively across executive leadership, engineering teams, customers, and industry partners.

A customer-first mindset focused on delivering industry-leading product quality, reliability, and performance.

This role offers a unique opportunity to define the future of memory validation for industry-leading FPGA products. As a Memory Validation Architect, you will influence product architecture, shape validation strategy across multiple generations, mentor engineering teams, and play a critical role in delivering innovative programmable solutions to customers worldwide.

We also offer incentive opportunities that reward employees based on individual and company performance.

$We use artificial intelligence to screen, assess, or select applicants for the position. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 15+ years of industry experience in memory subsystem architecture, silicon validation, high-speed interface development, or a related field; Memory controller architecture or DDR PHY architecture or Memory initialization and training or DDR calibration algorithms or JEDEC memory specifications or Memory timing analysis and scheduling

• 8+ years of experience performing board-level signal integrity (SI), power integrity (PI), timing analysis, or high-speed memory channel validation.
• 5+ years of hands-on experience using high-speed laboratory validation equipment such as oscilloscopes, protocol analyzers, logic analyzers, Bit Error Rate Testers (BERTs), traffic generators, or equivalent debugging tools.
• 5+ years of programming or automation experience using Python, C/C++, or similar scripting or programming languages to develop validation, debug, characterization, or test automation solutions.
• 5+ years of experience leading cross-functional technical projects involving at least three of the following disciplines: architecture, RTL design, firmware, silicon validation, software development, customer engineering, or product engineering.

Experience with FPGA or ASIC memory subsystem development.

Strong understanding of PCIe, CXL, AXI, AMBA, and coherent interconnect architectures.

Demonstrated success influencing architecture decisions across multiple product generations.

Regular Shift:

Shift 1 (United States of America) Primary Location:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.