Principal RFIC Layout Designer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we’re Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you’re excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking an experienced RFIC Layout Designer to drive the physical implementation of advanced RF and mixed-signal integrated circuits for next-generation satellite communication systems. This role requires deep expertise in FinFET technologies, hands‑on ownership of top-level SoC layout integration, and proven experience leading both internal and external layout teams. The ideal candidate combines strong technical execution with leadership, enabling high-quality, schedule-driven delivery across complex, multi-disciplinary silicon programs. Responsibilities Lead the end-to-end layout implementation of RF and mixed-signal blocks in advanced FinFET process nodes. Own top-level layout integration for complex SoCs, including floorplanning, hierarchy definition, power distribution, and physical assembly. Drive layout strategies to meet performance, area, power, reliability, and manufacturability targets. Ensure robust implementation of matching and symmetry for sensitive RF/analog structures, and high-frequency routing and parasitic control. Lead shielding, isolation, and substrate noise mitigation methodologies. Ensure robust implementation of EM/IR, ESD, latch-up, and reliability considerations. Define layout methodologies, guidelines, and best practices for RFIC and mixed-signal design in FinFET technologies. Plan and manage layout schedules, milestones, and deliverables aligned with tapeout goals. Collaborate closely with RF/analog designers, digital implementation teams, package/PCB engineers, and CAD to ensure seamless integration. Manage and coordinate work with external layout vendors/contractors, including task definition, quality control, and schedule tracking. Establish review processes (layout reviews, signoff checks, and quality metrics) to ensure first-pass silicon success. Drive full-chip physical signoff, including DRC/LVS/ERC closure, EM/IR and reliability verification. Own tapeout readiness and interface with foundry and EDA partners as needed. Qualifications 10+ years of RF/analog/mixed-signal layout experience, including leadership responsibilities. Extensive hands‑on experience with advanced FinFET process technologies (≤16nm preferred). Proven track record of top-level SoC layout integration and successful silicon tapeouts. Experience collaborating with distributed teams, including management of external layout vendors. Deep understanding of RF and analog layout techniques and device physics, including high-frequency effects, parasitics, and isolation strategies. Extensive hands‑on experience with power planning and full-chip physical architecture. Strong proficiency with industry-standard tools. Nice to Have Experience with high-frequency RF systems for wireless or satellite communications. Familiarity with multi-chip module (MCM) or advanced packaging considerations. Experience working on large mixed-signal SoCs with significant digital content. Exposure to reliability requirements for space or high-reliability applications. Experience developing methodologies in a high-growth environment. Compensation And Benefits Base salary range for this role is $140,000 – $200,000 + equity in the company Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. #J-18808-Ljbffr K2 Space Corporation