Design Engineer V

Job Description Job Description At-a-Glance Are you ready to build your career by joining a leading global provider of product engineering and semiconductor design services. If so, our client is hiring a Design Engineer V. Position Type Contract Onsite Location: Sunnyvale, CA Required Education: Bachelor’s degree. Senior-level experience with Cadence Allegro (v21). Rigid-flex and flexible circuit design experience. HDI (high-density interconnect) PCB design experience. Strong overall PCB layout/design background for complex boards. 8+ years of experience in complex PCB Design. 5+ years of experience using Allegro PCB Design Tools (version 23.1 or newer). Strong understanding of the mechanical aspects of electronics design. Excellent communication skills. Proficiency with Microsoft Office tools. Responsibilities Project Management & Execution: Lead designs from kick-off through tape-out, encompassing rigid, rigid-flex, and flex PCBs for both product and non-product/test projects. Proactively schedule and drive project meetings (Kick-off, Placement, Constraint, and Design Reviews) to ensure design verification using Design Traveler document. Create and modify engineering tool project templates, meta-data, configuration data, and rules. Technical Expertise & Problem Solving: Apply a solid understanding of electrical engineering principles, particularly for power distribution, high-speed circuits, and RF signals. Identify project execution risks or slowdowns proactively and collaborate with managers and/or technical program managers to propose alternative PCB development workflow solutions. Understand and propose practical fit and function solutions related to miniaturization concepts. Cross-Functional Collaboration & Supplier Engagement: Proactively partner with EE Leads, Mechanical Engineering, TPMs, and other cross-functional teams (XFNs) to resolve design issues. Work with internal DFM engineers to confirm supplier requirements at project launch. Engage with external suppliers and Supplier Quality/Process Engineering (SQE/PE) to resolve DFM issues and ensure high-yield builds. #J-18808-Ljbffr Hired by Matrix