Senior RTL Design Engineer - RISC-V CPU Frontend
SiFive, Inc.
SiFive, Inc. in Santa Clara is seeking an experienced engineer to architect and implement features in RISC-V CPU core generators. This role demands proficiency in CPU RTL design and solid software engineering skills. A comprehensive benefits package is included, reflecting SiFive's commitment to employee well-being. The ideal candidate will have a relevant degree and a collaborative mindset, contributing to a culture of high-quality design and teamwork. #J-18808-Ljbffr SiFive, Inc.
Vacancy posted 4 days ago
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