Senior/Staff Design Engineer

About MIPS @ GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With the addition of the MIPS team, GF now offers a rich portfolio of RISC‑V CPUs, especially AI‑enabled processors for the Physical AI world. Summary of Role We are seeking recent graduates who are eager to become world‑class CPU IP Design Engineers. The role involves developing and owning RTL development of our latest AI‑enabled RISC‑V CPU core. The candidate will be responsible for all aspects of the design, including functional features, performance, power, and area. Essential Responsibilities Drive the micro-architecture and design of critical blocks of the CPU core. Design of RISC‑V Vector CPU core and its custom extensions. Design of AI‑enabled matrix engine to augment the Vector CPU. Explore high-performance strategies working with the CPU modeling team. Perform micro-architecture development and specification from early high-level architectural exploration through microarchitectural research to detailed specifications. Configure design features. Develop, assess, and refine RTL design to target power, performance, area, and timing goals. Perform functional verification support and assist in the design verification strategy. Assist with the verification of RTL design performance goals. Partner with a cross‑functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power. Other Responsibilities Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. Required Qualifications Knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core. Knowledge of microprocessor architecture, including instruction fetch and decode, branch prediction techniques; instruction scheduling, register renaming, reorder buffer (ROB); out-of-order execution; integer and floating-point execution; load/store execution; instruction and data prefetch; vector datapath; cache and memory subsystems. Experience with SystemVerilog, Verilog, or VHDL. Experience with simulators and waveform debugging tools. Knowledge of logic design principles along with timing and power implications. Bachelor’s degree with 3–7 years of experience or Master’s degree with 2–5 years of experience. Preferred Qualifications Experience designing RISC‑V, ARM, and/or MIPS CPUs. Experience with hardware multi-threading, virtualization, and SIMD designs. Experience with vector and matrix-enabled CPUs, preferably RISC‑V processors. Understanding of high-performance techniques and trade-offs in a CPU microarchitecture. Experience with low-power microarchitecture techniques. Experience using a scripting language such as Perl or Python. Knowledge of cache coherency and memory consistency. Understanding of CPU integration at SoC level. Understanding of Safety and Security microarchitecture. Expected Salary Range $69,000.00 - $202,000.00 (exact salary determined based on qualifications, experience, and location). Accommodation If you need a reasonable accommodation for any part of the employment process, please contact us by email at View email address on click.appcast.io and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Equal Opportunity GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. All policies and processes that pertain to employees, including recruitment, selection, training, utilization, promotion, compensation, benefits, etc., are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law. #J-18808-Ljbffr MIPS Holding Inc