Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Senior RTL Design Engineer - Space ASICs for Global Connectivity

SPACE EXPLORATION TECHNOLOGIES CORP

SPACE EXPLORATION TECHNOLOGIES CORP is looking for a motivated SR. RTL DESIGN ENGINEER in Sunnyvale, CA to develop cutting-edge ASICs for Starlink. This role includes responsibilities in evaluating design architectures, implementing RTL in Verilog/System Verilog, and collaborating with verification teams. The candidate must have a Bachelor's degree, 5+ years in RTL implementation, and the ability to tackle complex engineering challenges. Enjoy a competitive salary package that includes comprehensive benefits and opportunities for long-term incentives. #J-18808-Ljbffr

Vacancy posted 10 hours ago
Similar jobs that could be interesting for youBased on the Senior RTL Design Engineer - Space ASICs for Global Connectivity in Sunnyvale, CA vacancy
  • $150k - $220k

     ...Description Ready to make connectivity from space universally...  ...fundamentally change the design, economics,...  ...intelligence that will expand global economies, protect...  ...We are seeking a Senior ASIC Design Engineer to join our processor...  ...the intersection of RTL design and functional... 
    Senior
    Full time
    Work at office
    Immediate start
    Visa sponsorship
    Night shift

    E-Space

    Saratoga, CA
    10 days ago
  • $170k - $230k

    SpaceX is seeking a Sr. SOC/ASIC Physical Design Engineer to develop next-generation silicon for space and ground infrastructures. You'll work with top engineers...  ...to enhance the Starlink network, enabling connectivity globally. Ideal candidates have a background in ASIC... 
    Senior

    jobr.pro

    Sunnyvale, CA
    2 days ago
  • $170k - $230k

     ...Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale,...  ...that allow users to connect within minutes of unboxing...  ...Starlink’s potential global impact and are...  ...silicon for deployment in space and ground infrastructures...  ...targets, and explore RTL/design tradeoffs... 
    Senior
    Permanent employment
    Temporary work
    Worldwide
    Weekend work

    SPACE EXPLORATION TECHNOLOGIES CORP

    Sunnyvale, CA
    3 days ago
  •  ...human life on Mars. SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)...  ...that allow users to connect within minutes of unboxing...  ...Starlink’s potential global impact and are looking...  ...product engineering, ASIC implementation). In...  ...ASICs for deployment in space and ground... 
    Senior
    Worldwide

    SpaceX

    Sunnyvale, CA
    2 days ago
  • $170k - $235k

     ...life on Mars. SR. RTL DESIGN ENGINEER (SILICON...  ...that allow users to connect within minutes of...  ...Starlink’s potential global impact and are looking...  ...product engineering, ASIC implementation)....  ...for deployment in space and ground infrastructures...  ...Design Engineer/Senior: $170,000.00 - $23... 
    Senior
    Permanent employment
    Temporary work
    Worldwide
    Weekend work

    SPACE EXPLORATION TECHNOLOGIES CORP

    Sunnyvale, CA
    18 hours ago
  • $126.7k - $190.1k

    Qualcomm is seeking a skilled ASIC designer to join their Santa Clara team. This role requires significant experience in micro-architecture and design integration, with hands-on responsibilities throughout the ASIC lifecycle. Successful candidates will collaborate closely... 
    Senior

    Qualcomm

    Santa Clara, CA
    2 days ago
  • $120k - $220k

    E-Space is looking for an experienced Physical Design Engineer to lead complex ASIC and SoC designs. With a focus on innovative satellite technology, you'll work with cutting-edge tools like Cadence Innovus. The role requires a minimum of 8 years of experience in physical... 
    Senior

    E-Space

    Saratoga, CA
    2 days ago
  • $150k - $220k

    E-Spac is seeking a Senior ASIC Design Engineer based in Saratoga, California, to lead the integration and verification of Arm processor IP for satellite...  ...7+ years of experience in ASIC/SoC design, proficiency in RTL design using SystemVerilog or VHDL, and familiarity with... 
    Senior

    E-Spac

    Saratoga, CA
    3 days ago
  • $136k - $218.5k

    NVIDIA Gruppe in Santa Clara is looking for a talented engineer to join their Clocks team. This role involves architecting clock domains...  ...Engineering or equivalent, 3+ years of experience in RTL design, strong skills in Python, and excellent interpersonal abilities... 
    Senior

    NVIDIA Gruppe

    Santa Clara, CA
    2 days ago
  • $170k - $235k

     ...company in Palo Alto is seeking a Sr. ASIC Design Engineer for the Starshield project, focusing on...  ...fields and over 5 years of experience in RTL/FPGA development. The position offers a...  ...vacation and medical coverage. #J-18808-Ljbffr SPACE EXPLORATION TECHNOLOGIES CORP
    Senior

    SPACE EXPLORATION TECHNOLOGIES CORP

    Palo Alto, CA
    1 day ago
  •  ...A leading semiconductor company is seeking a Senior ASIC Design Engineer to join their Silicon Design team in San Jose, CA. The ideal candidate will oversee the complete RTL design lifecycle for next-generation embedded products, ensuring design quality and timing closure... 
    Senior

    Advanced Micro Devices , Inc.

    San Jose, CA
    3 days ago
  • $136k - $265k

     ...NVIDIA Gruppe is seeking a Senior ASIC Design Engineer for its Memory Controller team in Santa Clara, California. This role involves collaboration with architects and engineers to design and verify micro-architectures for memory subsystems. The ideal candidate will have... 
    Senior

    NVIDIA Gruppe

    Santa Clara, CA
    3 days ago
  •  ...SPACE EXPLORATION TECHNOLOGIES CORP (SpaceX) in Sunnyvale, CA is looking for a Sr. SOC/ASIC Physical Design Engineer. The role involves developing cutting-edge silicon for deployment in space and improving physical design methodologies to enhance the Starlink network.... 
    Senior

    SPACE EXPLORATION TECHNOLOGIES CORP

    Sunnyvale, CA
    3 days ago
  • $181.1k - $318.4k

     ...Sunnyvale, California is seeking a Wireless Design Engineer to join their wireless silicon development team. This role involves RTL design of wireless MACs, creating specifications...  ..., and ensuring high performance low power ASIC designs. The ideal candidate should have at... 
    Senior

    Apple Inc.

    Sunnyvale, CA
    4 days ago
  • Google Inc. is seeking an experienced engineer in Sunnyvale, CA to lead the high-performance ASIC design and RTL execution for AI hardware. The successful candidate will collaborate with system architects and software teams, owning the complete RTL lifecycle to ensure... 
    Senior

    Google Inc.

    Sunnyvale, CA
    3 days ago
  •  ...functional, physical and testing design requirements. Engage with...  ...implement new Clocking topologies in RTL. Collaborate with Physical...  ...in end-to-end cycle of ASIC execution starting from micro‑...  ...Qualifications BS in Electrical Engineering or equivalent experience (MS preferred... 
    Senior
    Work experience placement

    NVIDIA Gruppe

    Santa Clara, CA
    2 days ago
  • $136k - $212.75k

     ...clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible...  .... The team collaborates with the front design team to understand the clocking requirements...  ...implement new Clocking topologies in RTL.* Collaborate with Physical design and... 
    Senior
    Work experience placement

    NVIDIA Corporation

    Santa Clara, CA
    18 hours ago
  • $136k - $218.5k

    We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading...  ...expected to come up with micro‑architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design... 
    Senior

    NVIDIA

    Santa Clara, CA
    18 hours ago
  •  ...NVIDIA Gruppe in Santa Clara is hiring an ASIC Design Engineer to develop cutting-edge SoC and GPU products. You will work with a talented engineering...  ...microarchitecture documents, implementing high-performance RTL, and collaborating with various teams. Ideal candidates hold... 

    NVIDIA Gruppe

    Santa Clara, CA
    4 days ago
  • $110k - $300k

     ...centers. Our talented team of engineers and industry‑leading executives...  ...is the place for you. Join our global team to shape the future of AI...  ...opportunities? Join our team! Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust... 

    TetraMem Inc

    San Jose, CA
    11 hours ago
  • $155k - $185k

     ...SPACE EXPLORATION TECHNOLOGIES CORP in Sunnyvale, CA is hiring a Physical Design Engineer II. The ideal candidate will focus on cutting-edge ASIC development for Starlink, leveraging their expertise in physical design methodologies. Responsibilities include ASIC design... 

    SPACE EXPLORATION TECHNOLOGIES CORP

    Sunnyvale, CA
    11 hours ago
  • $136k - $218.5k

     ...NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! What You’ll Be Doing: Collaborate with architects, software engineers...  ...responsible for micro-architecture and design, including RTL design, synthesis, functional verification, and timing... 
    Senior

    NVIDIA Gruppe

    Santa Clara, CA
    3 days ago
  • $128k - $312k

     ...innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI...  ...paths within our custom ASICs. This role is located in...  ...and deliver high‑quality RTL designs optimized for AI...  ...ASICs, ensuring seamless connectivity and high‑throughput data... 
    Hourly pay
    Full time
    Temporary work
    Flexible hours

    Tesla Motors, Inc.

    Palo Alto, CA
    2 days ago
  • Advanced Micro Devices is seeking a Senior ASIC Design Engineer in Santa Clara, CA, to architect and design DPU ASICs for AI networking workloads....  ...candidate will have extensive experience in ASIC design, strong RTL skills, and a solid background in networking architectures.... 
    Senior

    Advanced Micro Devices

    Santa Clara, CA
    2 days ago
  • Hewlett Packard Enterprise Development LP is seeking a Principal Physical Design Engineer to develop advanced ASIC design methodologies in Sunnyvale, California. This key role involves enhancing RTL-to-GDS flows, providing physical design support, and ensuring... 
    Senior

    Hewlett Packard Enterprise Development LP

    Sunnyvale, CA
    18 hours ago
  • $138k - $198k

    RTL Design Engineer, TPU Integration and Automation Google, Sunnyvale, CA, USA...  .... 4 years of experience in ASIC design, design automation,...  ...level IP assembly, focusing on connectivity and configuration. Automate...  ...computing power to global services, and providing the... 
    Worldwide

    Google Inc.

    Sunnyvale, CA
    3 days ago
  • MatX Inc. is looking for a Physical Design CAD Engineer to enhance our silicon development. The role requires...  ...improving the Physical Design flow from RTL to GDSII, ensuring high-performance outcomes. Strong programming and ASIC methodologies expertise are essential. This... 
    Senior

    MatX Inc.

    Mountain View, CA
    1 day ago
  • $180k - $230k

     ...ushers in a new era of car connectivity and capabilities. We...  ...looking for talented engineers and leaders who have...  ...and want to drive their design from concept to...  ...to their next car. Senior ASIC Front-End Design Engineer...  ...architecture specification, RTL, verification,... 
    Senior
    Remote work
    Flexible hours

    Ethernovia

    San Jose, CA
    3 days ago
  •  ...Advanced Micro Devices in Santa Clara is looking for a skilled engineer to contribute to ASIC design for high-performance network chips. You'll work within the NTSG ASIC Design Team focusing on achieving first-pass silicon success through collaboration with architecture... 
    Senior

    Advanced Micro Devices , Inc.

    Santa Clara, CA
    3 days ago
  • $153.2k - $229.8k

     ...Qualcomm is seeking an experienced ASIC Engineer to drive the development of high-performance IP for world-class products in Santa Clara,...  ...candidate should have at least 4 years of experience in ASIC design and possess a relevant degree. Responsibilities include defining... 
    Senior

    Qualcomm

    Santa Clara, CA
    3 days ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Senior RTL Design Engineer - Space ASICs for Global Connectivity. Be the first to apply!