Senior Staff Design Verification Engineer

Location Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. Design Verification Engineer, Senior Staff Responsible for developing and executing SoC verification environments from architecture to tape‑out and bring‑up. Will contribute to the design and testing of a highly programmable in‑memory computing architecture for cloud and edge applications. What you will bring BS in Electrical Engineering, Computer Science or related field with 12+ years of industry experience OR MS preferred with 7+ years experience. Experience in SoC verification cycle from architecture to tape‑out to bring‑up. Good knowledge of verification methodologies such as UVM/OVM. Hands‑on ASIC‑SoC design verification tests and debug experience. Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology. Good problem‑solving skills and passion for tackling challenges in the AI domain. Experience with SystemVerilog and verification methodology (UVM/OVM/VMM). Passionate about AI and thriving in a fast‑paced, dynamic startup culture. Preferred Experience with C/C++ and SystemC. Successfully led creation/implementation of multiple SoC verification environments and tape‑out efforts. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. #J-18808-Ljbffr