Power‑Management CPU Architect & RTL Design Engineer
$158.76k - $194.04kSiFive, Inc.
SiFive, Inc. seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer in Santa Clara to design leading CPU and interconnect IP. You will collaborate with various teams to define specifications and optimize power-management features, ensuring high-quality design and performance. The ideal candidate will have a BS/MS in EE, CE, or CS, and be proficient in RTL design with 3+ years experience in CPU or SoC design. The role offers a salary range of $158,760 – $194,040 and comprehensive benefits. #J-18808-Ljbffr SiFive, Inc.
Vacancy posted 1 day ago
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