Power & Clocking RTL Design Engineer (RISC-V)
Socket.dev
SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to craft the central nervous system for cutting-edge RISC-V CPU and SoC IP. You will design configurable power management, reset, and clocking solutions as part of a dynamic team delivering high-performance hardware that pairs with software-driven agility. The role requires hands-on RTL work in Verilog/SystemVerilog, a background in CPU/SoC development from architecture to tapeout, and collaboration with #J-18808-Ljbffr Socket.dev
Vacancy posted 4 days ago
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