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Physical Design Engineer

Mirafra Technologies

Key Responsibilities

  • Deeply understand what is involved in physical design
  • Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
  • improve CAD infrastructure
  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
  • Drive dashboards that show the convergence of projects related to PD
  • Optimize tool flows, working with EDA vendors to incorporate the latest features
  • Accountable for block level closure
  • Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

  • 5-10+ years of previous experience with PD
  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
  • Experience with back-end design and timing closure on advanced process nodes (5nm
  • and below)
  • Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
  • automated RTL-to-GDSII flows
  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
  • Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
  • routing, IR drop, and EM/antenna analysis
  • Deeply creative and able to think from first principles

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures
  • Ability to program with Python or another scripting language
  • Familiarity with AI tools for programming/coding
  • Startup experience or comfort working in fast-paced environments

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