Senior ASIC RTL Designer - Microarchitecture & SystemVerilog
$157.3k - $212.8kJobleads-US
Annapurna Labs (U.S.) Inc. in Cupertino, CA, is hiring for an ASIC II role (AMZ27538.3) to design and optimize hardware for cloud infrastructures, including AWS Inferentia.
The position runs 40 hours per week, 8:00am-5:00pm, with a salary range of $157,300–$212,800; base pay varies by experience and market location. The ideal candidate holds a bachelor's degree in CS or engineering and 3+ years in design/architecture, SystemVerilog RTL, and code-quality tools.
#J-18808-Ljbffr Jobleads-USVacancy posted 2 days ago
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