Senior RTL/SoC Design Engineer for AI & In-Memory IP
TetraMem - Accelerate The World
TetraMem in San Jose, CA is seeking a senior RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs. You will integrate IP blocks, perform PPA analysis, collaborate with backend, and drive tapeout readiness while developing reusable IPs for AI and in-memory computing. The role includes mentoring junior engineers, contributing to design reviews, and staying current with RTL methodologies to improve product quality.
#J-18808-LjbffrVacancy posted 2 days ago
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