Senior RTL Design Engineer - Ultra-Low-Power SoC & NoC
Efficient Computer
Efficient Computer seeks a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC, focusing on on-chip interconnect and memory interfaces, low-power logic, and peripheral IP. You will collaborate with architects, DV, physical design, and firmware to tape out a leading ultra-low-power fabric. This unique role joins a growing HW engineering team moving from initial product development to market release and scaled production.
#J-18808-Ljbffr$180k - $245k
...are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC: the compute fabric... ...memory interfaces, low-power and always-on... ...an industry-leading ultra-low-power SoC. This... ..., on-chip networks/NoC, memory interfaces,...Night shiftSenior- ...NVIDIA Corporation is seeking a Senior ASIC Design Engineer in Santa Clara, CA to design... ...high‑performance GPU and SoC sub-systems. You will own micro-architecture, write RTL, and ensure fully verified, timing... ...aggressive performance and power targets for leading AI and...Senior
- ...technology has the power to solve the world’... ...future. Whether you’re designing next-gen processors... ...? Join AMD’s CPU engineering team and help shape... ...definition and RTL development through... ...processor architecture, low-power design, and... ...for processors, SoCs, or complex IP blocks...Suggested
$138k - $206k
...technology solutions power the tools you use... ...whose innovative designs are pushing the... ...and software engineers to identify and address... ...computing IP and SoC partitions from RTL netlist to GDSII,... ...controllers, NoC, and high-bandwidth... ...) development, low-power design (UPF...Night shiftSeniorWork at officeFlexible hours- ..., California is seeking a senior ASIC physical design engineer to execute synthesis, PnR,... ...assigned partitions of an SoC under strict schedules. You... ...with architects, RTL designers, and DFT teams to... ...LEC signoffs, and ensure low-power design techniques while refining...Senior
- ...TetraMem in San Jose, CA is seeking a senior RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs. You will integrate IP blocks, perform PPA analysis, collaborate with backend, and drive tapeout...Senior
$280k
RTL IC Design Engineer (Senior, Staff or Principal)Compensation:For Senior - up to approx... ...-performance silicon that powers next-generation AI, machine... ..., pipelined architectures, low-power designs, multi-clock... ...designing ASICs or complex SoCs.Strong understanding of...Senior- ...Cadence Design Systems, Inc. in San Jose is seeking a hardware verification engineer to implement and verify high-capacitance Palladium and Protium SOC tape-out. You will contribute to RTL synthesis, clock tree building, timing closure and cross-functional design reviews...Senior
- ...Job Description Design Engineer Build the Next Generation... ...high-performance SoC technologies. Our products power data-intensive applications... ...architecture, and RTL development. As... ...high-speed, low-power SoC designs... ...opportunities into Senior, Staff, and Principal...Ongoing contractLocal areaWork visa
- ...Baya Systems seeks a Principal Engineer-Physical Design for a fully remote role... ...US. The candidate will own RTL to GDS physical implementation... ...tree synthesis, timing and power closure, and PDV activities.... ...performance, power-efficient SoC designs is essential. Qualifications...Remote work
- ...Apple Inc. is seeking a hardware verification engineer in Cupertino, CA to verify low power aspects of Apple SOCs. You will develop test plans, create directed and... ...verify power state transitions. Collaboration with design, architecture, and software teams is essential,...
$136k - $218.5k
NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate... ...build cutting-edge GPUs and SOCs that power everything from AI to gaming! As a... ...improvementsEnsure high-quality RTL delivery to the physical design team with...SeniorFull time$150k - $220k
...building a highly-advanced low Earth orbit (LEO)... ...change the design, economics, manufacturing... ...seeking an experienced SoC Power Architecture Engineer to define, design, and... ...aggressive duty cycling, ultra-low standby power,... ...ensure consistency with RTL implementation ·...Night shiftFull timeWork at officeImmediate startVisa sponsorship$182k - $319k
...hardware that we designed, developed, manufactured... ...server providers engineering solutions for this... ...firsthand the power of our people - people... ...together.The Senior Principal, Design... ...with high power, low noise, efficient,... ...>500W) as well as ultra-low noise power delivery...SeniorLocal area- ...Apple Inc. in Cupertino, California, is seeking a Senior IC Design Engineer to lead power reduction and physical design for advanced node SoCs. You will perform static and dynamic power analysis, implement low power techniques, fix violations, and drive tape-out readiness...
- ...can help you find the best job for you. Role: RTL Design Engineer - Wireless SoC Location: Remote Duration: 6 months Required Skills... ...for SoC components including interfaces, clock/reset, power management, and debug logic Work with internal and...Permanent employmentContract workRemote work
- ...Qualcomm Technologies, Inc. in Santa Clara, California is seeking a Physical Design Engineer to contribute across ASIC/SoC projects, including floorplanning, CTS, and low-power strategies. The role involves executing the full physical design flow, collaborating with cross...Senior
- ...Sunnyvale, CA is seeking an experienced ASIC Design Engineer to develop custom silicon for data-... ...microarchitecture, write SystemVerilog RTL, and collaborate across software, architecture... ...design teams. The role emphasizes power, performance, and area optimizations, validation...Senior
$135.9k - $201.13k
..., Your ImpactAs a Senior Staff Digital ASIC Design Engineer at Marvell, you will... ...that enable ultra high bandwidth, low latency data movement... ...silicon solutions powering the global AI infrastructure... ...teams to define SoC‑level... ...and IP blocks.Own RTL development for assigned...SeniorPermanent employmentFull timeInternshipWork from home$110k - $300k
...Responsibilities Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient... ...requirements, conducting Power, Performance, and Area (PPA) analysis... ...guiding and coaching junior engineers, sharing expertise and best...Local area$150k - $220k
...a highly-advanced low Earth orbit (LEO)... ...fundamentally change the design, economics,... ...We are seeking a Senior ASIC Design Engineer to join our processor... ...intersection of RTL design and functional... ...Collaborate with SoC architects to... ...Knowledge of low-power design techniques...Night shiftSeniorFull timeWork at officeImmediate startVisa sponsorship- ...Job Title: SoC Design Verification Engineer Location: San Jose, CA Job Description... ...silicon meets performance, power, and functionality targets.... ...with architecture, RTL, and software teams... ...architecture, memory hierarchy, NoC/interconnect Expertise...Night shift
$160k - $275k
...silicon micro-architects and design engineers to join our team as we... ...and maintain power estimation methodologies for AI accelerator SoCs.Build and calibrate energy... ...target definition.Perform RTL, gate-level, and post-... ...design.Experience with ASIC low-power design techniques...SeniorDaily paidFull timeWork experience placementWork at officeLocal areaRemote workMonday to FridayFlexible hours- ...s wireless chip powers connectivity across... ...? Our wireless SOC organization... ...energy-efficient design and new technologies... .../PHY/MAC, VLSI/RTL design and... ...Validation, and FW/SW engineering. As a Wireless... ...actually calls for. Low power is part of... ..., bus fabric/NOC, or AHB/AXI-...Night shift
- ...memory solutions is seeking a Sr. Staff Physical Design Engineer to lead RTL-to-GDS implementation for advanced-node SoCs. You will guide synthesis, placement, CTS, and... ...while collaborating with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon...Senior
$220.92k - $311.89k
...highly experienced a Director, SoC Design Engineering, to lead the functional... ...Collaborate with SoC architects, RTL designers, and firmware teams... ...such as PCIe, DDR, AXI, CHI, or NoC.- Hands-on experience with... ...experience- Familiarity with power intent verification (UPF) and...Night shiftFull timeWork experience placementLocal areaImmediate startWorldwideShift work$168k - $264.5k
We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing Power Circuits Solutions Group. If you are looking for a challenging... ...level understanding of power delivery solutions for SoCs, including thermal constraints, package and board...SeniorFull time$110.6k - $140k
...control or processing function design and verificationHigh speed... ...design flow, including verilog RTL coding/simulation, synthesis,... ...formalityKnowledge of high performance and low power design techniques.Knowledge of... ...platforms.Knowledge of SOC architecture.Knowledge of...$136k - $218.5k
The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board,... ...squarely in scope.Multi-rail, multi-domain PDN ownership at SoC level — die + package + board co-optimization in...SeniorFull timeLive in$121.9k - $195k
...delivering high-quality SystemVerilog RTL in advanced process nodes (5nm... ...a deep understanding of RTL Design, PPA optimization, clock... ...crossing (CDC) analysis, and low-power design techniques.Experience:BSEE... ...experience with a focus on SoC integration, LPDDR5/6, DDR4/5...Full timeLocal area
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