Design-for-Test Engineer — RF/SoC Chip Validation (6m)
$100 - $130 per hourJobleads-US
Norland Group in San Jose, CA is seeking a Design-for-Test contractor to test and validate the next generation chips. You will work with Front End and Physical Design teams to implement DFT and test designs affecting RF and Bluetooth/Wireless LAN chipsets.
Requirements include 5+ years of DFT experience, excellent debugging skills, and the ability to work independently. The role is a 6-month contract with a pay rate of $100–$130 per hour.
#J-18808-Ljbffr Jobleads-USVacancy posted 1 day ago
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