Sr. Timing Methodology Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: In this senior position, you will be defining, developing, and driving timing methodologies across the Adaptive and Embedded Computing Group. You will work closely with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class PPA. You will bring your experience and expertise to solve the teams most pressing challenges in sign-off and modeling methodologies at 2nm and beyond on monolithic and 2.5/3DIC adaptive SOCs and FPGAs. Your solutions will enable products to compete in markets from the edge to the cloud while pushing the limits of performance and efficiency. THE PERSON: You are detailed oriented, possessing effective communication skills, and an experienced problem solver. You are passionate about optimizing for power, performance and area while meeting schedules and managing cost. You embrace cross-functional collaboration and continuous learning. You are comfortable in converting high level requirements from product planning, foundry, and other stakeholders into a set of methodologies and guidelines for the design community.KEY RESPONSIBILITIES: Define, develop, optimize and drive design, timing and power methodologies for advance process nodes.Collaborate with implementation and sign-off teams.Collaborate with CAD, power integrity, foundry teams and EDA vendors to understand margins and sign-off risks and develop mitigation strategies.PREFERRED EXPERIENCE: Experienced custom, physical design and/or sign-off engineer Expert user of industry-standard physical design, analysis, and sign-off toolsExperience with FPGA implementation tools.Experience advocating for technical solutions in a collaborative team environment.Excellent communication and collaboration skillsGood programming skills (Python, Perl, Tcl)ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION:San Jose, CAThis role is not eligible for visa sponsorship.#LI-SL2#LI-HYBRDBenefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.