Technical Staff Engineer - Verification

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a Technical Staff Engineer – Verification

Job Description:

Job Type: Fulltime

Job Location: Chandler, AZ (Preferred) or San Jose, CA or Roseville, CA

Work Schedule: Onsite/Hybrid 3 days onsite

The FPGA Business Unit team is seeking an experienced and innovative verification engineer to work on the verification of our next generation, highly secure, low-power FPGA device products.

Key Responsibilities:

• Verification of complex subsystems and SoC using an optimal combination of constrained random, formal and C based verification methodologies.
• Develop and maintain highly reusable UVM based test benches and verification environments.
• Involve in RTL, power aware and gate level verification.
• Contribute to quality and productivity be using AI/ML-enabled verification methodologies
• Collaborate with emulation and hardware prototyping teams to define a unified verification methodology .
• Collaborate with architecture and design teams to ensure seamless execution and first-silicon success.
• Mentor junior team members.

Required Qualifications:

• 12+ years in functional verification of complex SoC designs
• Expertise in System Verilog, UVM , formal verification methodologies
• Proven experience in methodology development and tool automation .
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
• Good understanding of SoC architectures – ARM/RISC-V
• Expertise in at least two of the following domains/peripherals
• CPU subsystems
• PCIe Gen3/Gen4/Gen5
• DDR4/DDR5, LPDDR4X
• MIPI DSI/CSI
• Ethernet MAC
• USB
• Security and cryptography IPs.
• Exposure to emulation , hardware prototyping and post-silicon debug
• Experience with FPGA-based acceleration platforms and simulation/emulation flows.

Software & Scripting: Python, TCL/TK, and C/C++ for automation and validation.

Tools:

• Familiarity with Siemens/Cadence/Synopsys verification suites
• Revision control systems (Git, Perforce, svn).

Preferred Skills:

• Highly Desirable: Strong understanding of FPGA architecture
• Experience with coverage-driven verification using ML-based optimizations .
• Experience in emulation , hardware prototyping and post-silicon debug ,
• Knowledge and exposure to complete SOC RTL to GDS to silicon release flow.

Required Education:

• BS or MS in Electrical/Electronic Engineering with 12+ years of experience

About Maxonic:

Since 2002 Maxonic has been at the forefront of connecting candidate strengths to client challenges. Our award winning, dedicated team of recruiting professionals are specialized by technology, are great listeners, and will seek to find a position that meets the long-term career needs of our candidates. We take pride in the over 10,000 candidates that we have placed, and the repeat business that we earn from our satisfied clients.

Interested in Applying?

• Please apply with your most current resume. Feel free to contact Saurav KP (View email address on apply.j-vers.com/View phone number on apply.j-vers.com) or Nina Schindler (View email address on apply.j-vers.com - 408-40-2299) for more details.