Physical Design Engineer

Job Title: Physical Design Engineer


City: Sunnyvale


State/Province: California


Posting Start Date: 5/28/26


Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients' most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at


Job Description:


Job Description

Job Overview:
We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning.

Key Responsibilities:
Block-Level Physical Design:
• Floorplanning & Partitioning - Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization - Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) - Design and optimize low-skew, high-performance clock networks.
• Routing & DRC Closure - Ensure successful global and detailed routing, meeting design rule constraints.
• Timing Closure - Work on setup/hold timing violations, signal integrity, and cross-talk reduction using static timing analysis (STA).
• Power & IR Drop Analysis - Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.
Top-Level Physical Design:
• Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution - Design robust clock trees and power delivery networks (PDN).
• Integration of IP & Sub-blocks - Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off - Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
• DFT Integration - Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.

Mandatory Skills: VLSI Board Design.


Experience: 5-8 Years.


The expected compensation for this role ranges from $60,000 to $148,500 .


Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.


Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.


Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.


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