Physical Design Engineer — SoC Floorplanning & Timing
$151.09k - $214.5kItlearn360
A leading technology company in Cupertino, CA, is seeking a Physical Design Engineer responsible for implementing design partitions for complex Systems-on-Chip. The ideal candidate will have a Master's degree in Electrical Engineering and at least 2 years of relevant experience. This role offers a competitive base salary ranging from $151,091 to $214,500, along with various benefits including medical coverage, retirement plans, and educational reimbursement. #J-18808-Ljbffr Itlearn360
$126.8k - $220.9k
...leading technology company is seeking a Physical Design Engineer to contribute to the design of high... ...GDSII. Responsibilities include generating timing constraints, building chip floor-plans,... ...Engineering and relevant experience in SoC designs. The base pay for this role...Suggested- A leading technology company in Sunnyvale is seeking a SoC Physical Design Engineer. Candidates should have a minimum of a BS degree and over 3 years of industry experience, focusing on partition-level P&R implementation. Responsibilities include working alongside the...Suggested
$181.1k - $318.4k
...responsible for the physical implementation of design partition(s) (from... ...for a highly complex SOC utilizing... ...and design goals. Timing, physical and electrical... ...implementation including floorplanning, clock and power... ...Electronics/Computer Engineering or related field....SuggestedRelocation$184.7k - $324.8k
...SoC Physical Design Engineer, PnR Imagine what you could do here! At Apple, new ideas have a way... ...meeting schedule and design goals. • Timing, physical and electrical verification... ...level P&R implementation including floorplanning, clock and power distribution, timing...SuggestedRelocation$116k - $189.75k
Responsibilities Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level... ...in Electrical or Computer Engineering (or equivalent experience)... ...optimization (e.g., synthesis, floorplanning, placement, CTS, routing,...Suggested$210k - $250k
...silicon and system designed from the ground up for... ...job completion times and tokens-per-second... ...and has a world-class engineering team with decades of... ...Responsibilities Define the Physical Assembly of SOC. Involving all... ...as P&R, timing, floorplan, clocking, electrical...$116k - $218.5k
NVIDIA Gruppe is looking for a talented engineer specialized in Physical Design and Timing Analysis. The successful candidate will be integral in driving the design and optimization of GPUs, CPUs, and SoCs, ensuring technical excellence through collaboration with multiple...- NVIDIA Corporation in Santa Clara is seeking a skilled engineer for a role focusing on Physical Design and timing analysis of GPUs, CPUs, and SoCs. Candidates should hold a Master's degree in Electrical or Computer Engineering and possess proficiency in Timing and Static...
$170k - $230k
SpaceX is seeking a Sr. SOC/ASIC Physical Design Engineer to develop next-generation silicon for space and ground infrastructures. You'll work with top engineers across various disciplines to enhance the Starlink network, enabling connectivity globally. Ideal candidates...- SPACE EXPLORATION TECHNOLOGIES CORP (SpaceX) in Sunnyvale, CA is looking for a Sr. SOC/ASIC Physical Design Engineer. The role involves developing cutting-edge silicon for deployment in space and improving physical design methodologies to enhance the Starlink network. Ideal...
$120k - $220k
...fundamentally change the design, economics,... ...WILL BE DOING: Lead physical design implementation from floorplanning through GDSII sign‑off for complex SoC blocks and full‑chip... ...and resolve timing violations through... ...and mentor junior engineers WHAT YOU BRING TO...Full timeWork at officeImmediate startVisa sponsorship- Staff / Senior Staff Physical Design Engineer - India Bolt Graphics is a semiconductor... ...critical role in achieving timing, power, and area (PPA)... ...flow: synthesis support, floorplanning, placement, CTS, routing, and... ...interfaces or complex SoCs (CPU/GPU/AI) Exposure to GLS...
- ...Title: Physical Design Engineer Location: 100% Remote Duration: Long Term Contract role... ..., design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical... ...to-end IP or integration of ASIC/SoC design Minimum Qualifications...Long term contractRemote work
$2,000 per month
...would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. Physical Design Engineer Etched is looking for... ...insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and...Work at officeRelocation package$126.8k - $220.9k
...United States Hardware Description As a Physical Design engineer you will contribute to all phases of... ...limited to: Generate block/chip level static timing constraints. Build full chip floor‑plan... ...design experience in high PHY and/or SOC designs. Deep Knowledge about industry...Relocation$141.8k - $258.6k
Apple Inc. in Santa Clara, California is seeking a Physical Design Engineer to join their Digital Design Engineering group. In this role, you will... ...and manage RTL to GDS steps such as physical synthesis and timing optimization. Candidates should have a BS and at least 2...$181.1k - $318.4k
...development team. Our wireless SoC organization is... ...highly energy-efficient design and new technologies... ...vertically integrated engineering team spanning RF/Analog... ...and thrive during crisis times, we encourage you to apply... ...structures, and with Physical design team to close and...Relocation$181.1k - $318.4k
...group, you’ll help design and manufacture... ..., system-on-chip (SoC)! You’ll ensure Apple... ...mix of strategic engineering along with hands-on... ...on experience in physical design and large chip... ...of the following: Floorplanning, Clock and Power... ...flows, and global timing verification Flows...Relocation$126.8k - $220.9k
...add something. Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign... ...to understand and develop flow, and with Physical design team to close and sign-off timing....Relocation$230k - $280k
...builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows... ...The Role As a member of our tight knit physical design team, you will be working on the design... ...involves a combination of traditional ASIC/SoC physical design skills, packaging, power...$136k - $264.5k
NVIDIA Corporation is seeking a Senior Physical Design Engineer located in Santa Clara, California. The successful candidate will drive physical design and timing, partner with mixed signal teams, and perform physical verification checks. Candidates should possess a BS...- NVIDIA Corporation is seeking a Senior Physical Design and Timing Engineer in Santa Clara, California. This role will focus on driving the physical design and timing of high-frequency and low-power CPUs and GPUs. The ideal candidate should have a BS in Electrical Engineering...
$168k - $264.5k
...for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join... ...graphics processors and SOCs. Key responsibility includes... ...methodologies for P&R, timing analysis and closure, convergence... ...projects along with chip floorplan, power and clock...$155k - $185k
...ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING) At the company we’... ...implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration...Permanent employmentTemporary workWorldwideWeekend work- ...Summary We are looking for an ASIC Floorplan Design Engineer (NCG) to design and implement the world’s leading SoC and GPU solutions,... ...with architects, design leads, physical and package leads to develop... ...improvement opportunities. Address timing and routing congestion issues...
$155k - $185k
Physical Design Engineer II (Silicon Engineering) Sunnyvale, CA SpaceX is actively developing technologies to enable... ...implementation steps (e.g., synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration...Permanent employmentTemporary workWorldwideWeekend work$256.05k - $361.48k
# **Welcome!**## .Senior Physical Design Integration Engineer page is loaded## Senior Physical... ..., floor planning, static timing analysis, power/clock... ...team is responsible for all SoC level physical design and... ...ASIC style design flows - floorplanning, clock construction, synthesis...Work experience placementLocal areaImmediate startFlexible hoursShift work$196k - $215k
...The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors... ...of computing with light! About this role We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of...Full timeTemporary workFlexible hours$120k - $192k
...Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with... ...), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family...Local areaRemote work$150.4k - $277.6k
...CPU Physical Design Engineer Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services... ...with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability Will work...Relocation
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