ASIC Physical Design and Timing Engineer - New College Grad 2026

Responsibilities Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. Play a pivotal role in the success of our innovative projects and advancement of our technology. Work in a cross‑functional environment interacting with multiple teams. Qualifications Master's degree or higher in Electrical or Computer Engineering (or equivalent experience). Proficiency in Timing and Static Timing Analysis (STA). Hands‑on experience in full‑chip/sub‑chip STA and timing convergence, timing constraints generation and management. Expertise with industry standard EDA and timing convergence tools. Preferred Qualifications / Ways to stand out Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors. Knowledge of deep sub‑micron process nodes. Proficiency in AI/LLM and programming languages. Experience in physical design and optimization (e.g., synthesis, floorplanning, placement, CTS, routing, power, etc.) is a plus. Benefits Base salary range: $116,000 - $189,750 (Level 2) and $136,000 - $218,500 (Level 3). You will also be eligible for equity and benefits. Equal Opportunity NVIDIA is committed to fostering an inclusive work environment and proudly is an equal opportunity employer. We do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Corporation