DFT Lead
Eridu
About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order-of-magnitude improvement in performance, unlock greater GPU utilization, and speed training job completion times and tokens‑per‑second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Responsibilities Define the DFT architecture of a multi-chip system SOC, involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD (ACJTAG/DCJTAG). Proficiency in synthesis design constraints (SDC). Prior experience with serializers/deserializers. Sound proficiency in either Mentor or Synopsys test tools. Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred. Fluent in RTL level and gate level simulation. Supervise ATPG generation and achieve high coverage goals for scan and speed scan. Qualifications Knowledge using synthesis, DFT & simulation CAD tools. Familiarity with logic and physical design principles to drive low‑power and higher‑performance designs. Fluency in scripting in Unix, Perl, Python, and TCL. Good understanding of device physics and experience in deep sub‑micron technologies (7nm or below). Prior exposure to EMIB architectures and bridge is a plus. Knowledge of Verilog and SystemVerilog. Excellent skills in problem solving, written and verbal communication, organization, and self‑motivation. Ability to work well in a team and be productive under aggressive schedules. Prior experience of multiple tapeouts in deep submicron 7nm or below is required. Master’s or bachelor’s degree in EE with a minimum of 15+ years of experience. Why Join Us? At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. The starting base salary for the selected candidate will be established based on relevant skills, experience, qualifications, location, market trends, and the compensation of employees in comparable roles. #J-18808-Ljbffr Eridu
$210k - $275k
...s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its... ...eridu.ai to learn more. Responsibilities Define the DFT architecture of a multi-chip system SOC. involving all aspects...Suggested- ...DFT Lead Full Time Opportunity in Saratoga, CA Responsibilities Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG). Proficiency in Synthesis design constraints....SuggestedFull time
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