Design Verification Engineer

Overview Senior Design Verification Engineer Job Summary We are seeking a Senior Design Verification Engineer to help verify and deliver next-generation AI SoC platforms. In this role, you will work closely with architects, RTL designers, software engineers, and system teams to ensure the correctness, performance, reliability, and safety of complex hardware systems. Responsibilities Develop and execute comprehensive verification plans for IP, subsystem, and SoC-level designs. Create constrained-random, directed, and coverage-driven test environments using SystemVerilog and UVM. Develop verification components including testbenches, monitors, scoreboards, assertions, and functional coverage models. Collaborate with architects and RTL designers to define verification strategies and ensure design intent is thoroughly validated. Debug complex design and system-level issues across simulation, emulation, and silicon bring-up environments. Drive functional and code coverage closure while maintaining high verification quality standards. Verify interactions between hardware, firmware, software, and AI workloads across the platform. Support performance, reliability, and safety validation efforts for advanced AI compute architectures. Contribute to verification methodology improvements, automation, and infrastructure development. Mentor junior verification engineers and promote verification best practices across the team. Required Qualifications Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 7+ years of ASIC or SoC design verification experience. Strong expertise in SystemVerilog and UVM verification methodologies. Experience developing constrained-random verification environments and coverage-driven verification strategies. Solid understanding of digital design, computer architecture, and RTL development. Experience debugging complex hardware issues and identifying root causes across multiple layers of the system. Proficiency with industry-standard simulation and waveform debug tools. Strong analytical, problem-solving, and communication skills. Preferred Qualifications Experience verifying AI/ML accelerators, high-performance computing systems, or data center SoCs. Knowledge of protocols such as AXI, PCIe, DDR, CXL, Ethernet, or other high-speed interfaces. Experience with formal verification, emulation, FPGA prototyping, or post-silicon validation. Familiarity with performance modeling and system-level architecture verification. Experience with embedded software, firmware, or HW/SW co-verification environments. Python, Perl, or other scripting experience for automation and workflow development. Skills soc design, UVM, SystemVerilog Experience Level Expert Level Job Type & Location This is a Permanent position based out of Santa Clara, CA. Pay and Benefits The pay range for this position is $200000.00 - $400000.00/yr. Medical, dental & vision Critical Illness, Accident, and Hospital 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available Life Insurance (Voluntary Life & AD&D for the employee and dependents) Short and long-term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a fully onsite position in Santa Clara, CA. The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. #J-18808-Ljbffr